在多處理機系統中有關記憶體子系統設計之研究及其模擬評估環境之研製

Abstract

共享記憶體多處理機系統在最近已成為計算機系統架構設計的一個重 要趨 勢。我們將設計一個共享記憶體多處理機系統模擬評估環境，來探 討多處理機 系統中共享記憶體子系統的重要設計議題。我們的模擬評估 環境是一種程式驅 動式模擬環境，它是由MINT所提供的記憶體參考產生 器與我們所設計的記憶 體子系統模擬器而組成的。我們所設計的記憶 體子系統模擬器，可提供兩層式 快取記憶體、Lockup-free Cache、記 憶體一致性模組、快取記憶體一致性協定 以及連結網路的模擬。 在本論文中，我們將利用此模擬評估環境，來探討有關記憶體一致性模 組、連接網路、雙鏈結目錄快取記憶體一致性協定以及遷移性分享的重要 設計 考量與方法。經過模擬評估之後，我們發現在釋放一致性模組中， 由於全域的 記憶體存取要求速率的提昇，使得網路頻寬需求也相對地提 昇。在雙鏈結目錄 結構下，由於採用循序的寫入失效/更新處理方式， 使得競爭更新式與寫入更新 式協定會造成嚴重的Critical Section釋放 延緩，而完全抹滅掉減少一致性失誤所帶來的好處。這些嚴重的Critical Section釋放延緩，經過我們的分析發現它主要是因遷移性分享所致。因 此，我們設計一個能減少遷移性分享負擔的方 法，經模擬評估之後， 發現此方法確實能有效地降低上述的Critical Section釋放延緩；使得競 爭更新式協定能正面地表現出因減少一致性失誤，而提昇整體 效能的好 處，甚至其效能優於寫入失效式協定。這些結果將提供系統設計者做 為 重要的參考。 Recently,shared-memory multiprocessor systems have become one of the design trends in computer system architectures. In the thesis,we developed a shared-memory multiprocessor simulation and evaluation environment to investigate the key design issues of shared-memory subsystem in multiprocessor system.Our simulation and evaluation environment is a program-driven simulation environment,it consists of a memory reference generator supported by MINT and a memory subsystem simulator that we design.The memory subsystem simulator supports several simulation modules,including two-level cache,lockup-free cache,memory consistency models, cache coherence protocols and interconnection network. With this simulation and evaluation environment,we investigated the key design considerations and methods about memory consistency models.interconnection network,doubly- linked directory cache coherence protocols and migratory sharing of shared memory block.Through a great many of simulation evaluations,we find that the network requirement will increase as a result of pipelining execution of memory accesses under release consistency model.Under the doubly-linked directory structure , the competitive-update protocol and write-update protocol will have the serious delay for releasing critical section as a result of adopting sequential write- invalidate/update,and the benefit for reducing coherence miss also will been hidden by the negative effect.Therefore,we design a method that can reduce the overhead of migratory sharing.Through simulation and evaluation results,we find that the method can effectively reduce the delay for releasing critical section and can effectively improve the performance of competitive-update protocol.Under our proposed method,the performance of competitive- update protocol can even better than the one of write- invalidate protocol..Theses important results can be referenced by the system designers.