一個在複雜和簡化指令集合併的架構中增進指令轉譯效能的方法

Abstract

本論文提出一個在複雜和簡化指令集合併的架構中增進指令轉譯效能 的方法. 這個方法就是設計一個新的指令解譯的架構, 包含新增一個指令 排班器和一個不同的轉譯器類型 (具有一個簡單, 一個適中和一個複雜的 轉譯器) . 其中, 增進指令轉譯效能就是要在每個時脈脈衝下增進指令被 轉譯的數目. 我們為這新的指令解譯架構建立一個模式, 作為實驗 組. 另外, 根據不同的指令解譯架構, 我們建立了三個模式作為對照組. 這四個模式是被用來評估不同的設計考量對轉譯效能的影響. 這些設計考 量包括指令混合類型, 指令相依情形, 轉譯器類型, 指令排班器的有無和 搜尋範圍的大小. 評估的結果顯示出實驗組的確比所有的對照組要有 較好的指令轉譯效能. 除此之外, 這些結果也顯示我們的新的指令解譯架 構比目前其他複雜和簡化指令集合併的架構在指令轉譯方面要表現的好. 除了評估指令轉譯效能的好壞外, 我們在論文中也探討了一些問題. 這些 問題主要是有關於排班器的最佳化和複雜度及中斷發生時的處理情形. This thesis proposes a method to improve the translating performance in the CISC/RISC bybrid processors. This method introduces the design of a newdecoder architecture which contains an instruction scheduler, a new translatortype with a combination of one simple, one general and one complex translators(1S+1G+1C). To improve the translating performance is to increase the number of CISC instructions per cycle. We build a decoder architecture model forthe proposed method to measure its translating performance. Besides, three different decoder architecture models are built for comparison. These four models are used to evaluate the effects of the different design issues for the translating performance. These issues include instruction mix, instruction dependencies,translator type, scheduler and search window size. The evaluationresults show that the model for the new decoder architecture with 1S+1G+1C translators and a scheduler performs better than other models. In addition, the results also show that the new decoder architecture has the ability to translate more instructions every cycle than other current CISC/RISC hybrid microprocessors do in average. Except evaluating the translating performance, we discuss some problems in the thesis. These problems are mainly about the optimization and complexity for the scheduler and the solutions for the interrupts occurrence.