CB-Power__以細胞單元為基礎的互補式金氧半電晶體靜態電路的功率特徵化及功率估測環境

Abstract

在此篇論文中,我們提出了以細胞單元為基礎的CMOS靜態電路的功率特徵 化分析與功率估測環境。在功率特徵化的過程中,輸入延遲,輸出負載,電 容連結效應以及邏輯狀態圖中各狀態點間的相依性都會被考慮。一個細胞 單元的功率消耗主要分為電容連結功率消耗,短路電路功率消耗,以及動態 功率消耗三部份,這三部份的功率方程式均由SPICE模擬結果求得。利用這 些功率方程式及Verilog_XL程式語言介面(PLI)裡的一些存取函式，我們 得到一個電路中所有細胞單元的輸出負載，輸入延遲，訊號機率及訊號轉 換密度。把這些結果輸入“以細胞單元為基礎的功率估測系統”（CBPE） 即可估測此電路的功率消耗。依照我們對一些標準電路所作的實驗結果， CB-Power在計算功率所花的中央處理單元時間上比SPICE快了兩次方以上 ，同時平均誤差小於7%。 In this thesis, we present CB-Power, a cell-based power characterization and estimation environment for static CMOS circuits. During the characterization, input slew, output loading, capacitive feedthrough effect and the logic state dependence of nodes in a cell are all taken into account. The characterization methodology separates the power consumption of a cell into three components, e.g., capacitive feedthrough power, short-circuit power and dynamic power. For each component, the power equation is derived from SPICE simulation results where the netlist is extracted from cell's layout. With these power equations and the access routines in Verilog_XL Programming Language Interface (PLI), we can obtain the output loading, input slew rate and input signal activities of each cell in a circuit. These results are applied to a Cell-Based Power Estimation (CBPE) system for power estimation. Experimental results on a set of ISCAS benchmark circuits shows that the power estimation based on our power modeling and characterization provides within 7% error of SPICE simulation on average while the CPU time consumed is more than two orders of magnitude less.