標題: 一種新式氧化層缺陷量測方法
A New Oxide Trap Characterization Technique
作者: 蔣汝平
Chiang, Lu-Ping
汪大暉
Tahui Wang
電子研究所
關鍵字: 熱載子效應;量測方法;能帶-能帶穿隧電流;氧化層缺陷充放電機制;時間常數;缺陷佔有率;Hot carrier effect;Characterization technique;Band-to band tunneling current;Oxide trap charging/dischraging mechanism;Time constant;Trap occupation
公開日期: 1995
摘要: 在此篇論文中,我們將藉由直接觀察能帶-能帶穿隧電流的時間變化情形以 發展出一套新的氧化層缺陷量測方法.同時我們將推導能帶-能帶暫態電流 和氧化層缺陷的密度及時間常數的關係的理論基礎.由理論上可以証明,此 種方法較傳統上以臨界電壓偏移的方法靈敏.穿隧電流和氧化層電荷成自 然指數的關係而臨界電壓只成線性關係.在實驗中,我們用兩種加壓方法, 分別是最大閘極電流入射的熱電子加壓及能帶-能帶穿隧所引發的熱電洞 注入的偏壓,如此可在氧化層內產生不同位置及能量的缺陷.在氧化層電子 放電機制方面,我們利用兩種放電方式:當汲極電壓不大時,暫態電流是由 於缺陷電子由缺陷中心發射至矽的導帶,當汲極較大時,暫態電流主要是由 於從基極來的熱電洞注入以及其所引發的熱電洞-缺陷結合所造成.我們的 研究發現,在薄的閘極氧化層時,電子發射時間和電場強度成一遞減函數, 這也証明了電子放電過程主要是因電場增強穿隧效應.在定量上的實驗與 計算的時間常數十分吻合.同時,我們利用一特殊的氧化層缺陷時間常數粹 取方法發現熱載子加壓所產生的氧化層缺陷最少有兩個時間常數,分別由 數秒到數十秒.此種現像主要是因為缺陷在能量上及空間上都是不均勻的 分佈.因為氧化層缺陷電子的時間常數相當長,氧化層缺陷電荷的佔有率將 無法馬上和直流的量測偏壓達成平衡.換句話說,缺陷的佔有率不但和量測 的偏壓有關,同時和元件偏壓的歷史有關.在此論文中,我們將觀察到一受 加壓後的元件氧化層缺陷電荷佔有率和對於元件特性的影響.由受加壓後 的元件藉由不同的充電條件來觀察元件特性的退化.我們對於兩種電子的 充電放電機制-電子熱捕捉和電場增強電子發射加以計算.在缺陷充電方 面,汲極-源極間電壓固定為3.5V,而改變閘極-源極電壓由1V到10V.我們的 研究發現,氧化層缺陷佔有率首先在低閘極電流時會隨閘極-源極電壓上升 而上升,在氧化層電場變大時隨閘極-源極電壓上升而減小.而在不同氧化 層缺陷佔有率對元件特性退化的影響方面,我們發現對於能帶-能帶穿隧電 流將可從0.2uA加強到1.3uA,臨界電壓偏移由0.22V到0.72V,汲極電流退化 由10.5%到16.5%. A New oxide trap characterization technique by directly monitoring the temporal evolution of a band-to-band tunneling current has been propoed. A especially designed experiment with a series of oxide trap charging and discharging conditions was performed. The theoretical basis of this measurement condition relatin the band-to-band tunneling current transient to oxide trap charge density and time constants was also derived. It can beshown, in theory, that this technique is much more sensitive to the variation of oxide charge then the threshold voltage shift method. The tunneling current exhibits an exponential dependence on oxide charge while the threshold voltage is only linearly related to oxide charge. Two hot carrier stress methods wereemployed in this work to generate oxide traps. One is hot electron stress a maximum gate current injection condition and the other is the band-to-band tunneling induced hot hole injection. It is believed that these two stress methods can generate oxide traps with different trap polarity and energy levels. Two oxide electron detrapping mechanisms were observed by utilizing the present method. At a modest Vds the band-to- band tunneling current transient is attributed to oxide electron emission from the traps to the Si conduction band while at a larger Vds the transient is mainly caused by hot hole injection from the Si substrate and subsequently the recombination of injected hole and trapped electrons.Our study reveals that in a thin gate oxide MOSFET(120A) the electron emission time is a strong decreasing function of an oxide field, which suggests that the oxide electron detrapping process is mainly via field enhanced tunneling. A quantitative agreement between the measured and the calculated trap time constants was achieved. Furthermore,based on a particular oxide trap time-constant extraction scheme developed inthis work, it was concluded that the hot carrier stress generated oxide traps contain at least two distinct time constant from seconds to several tens of seconds. The dispersion of field-dependent trap time constant is realized due to the nonuniform energetic and/or spatial distribution of the traps.Because of the long oxide trap time constants, the charge occupation of oxide traps cannot vary with a DC measurement instantaniously. In other ords, the trap occupation is not only dependent on a measurement bias but also dependent on a device bias history. The influence of oxide trap charge occupation on device characteristics in a hot carrier stressed n-MOSFET has been investigated.The post-stress device performance degradation was measured under various oxide trap filling conditions. The effects of two electron trapping/ detrapping mechanisms, electron thermal capture and field- enhanced electron emission, ontrap electron electron occupation were evaluated. In trap filling, The Vds wasfixed at 3.5V while the Vgs was varied from 1V to 10V. Our study shows that the oxide trap occupation first increases with Vgs at a low gate current level and then decreases with Vgs at a large oxide field. A remarkable variation of device performance degradation in a stressed n-MOSFET was obtained due to different oxide trap occupation, for example, a band-to-band tunneling current enhancement from 0.2uA to 1.3uA, a threshold voltage shift from 0.22V to 0.72Vand a drain current reducton from 10.5% to 16.5%.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT840430009
http://hdl.handle.net/11536/60606
顯示於類別:畢業論文