非同步傳輸模式交換系統之共享緩衝器與其控制單元

Abstract

本篇論文擬設計一非同步傳輸模式交換系統之共享緩衝器與其控制 單元。此交換系統具有32個輸入埠與32個輸出埠，每個埠的速度可達155 Mb/s。採用共享緩衝器的優點為所有之輸出埠皆共用一組記憶體，因而提 高記憶體之使用率，降低所需記憶體之總數。此交換系統共可儲存4096個 晶格（cell），因此在不同的網路狀況下皆可達到低晶格遺失率的要求。 一個交換系統是由八個SBF-VLSI及一個控制單元（CTRL-VLSI）所組成。 每個SBF-VLSI處理一個位元組（byte）中的位元（bit）。這些VLSI可整 合在一塊PC板上構成一個32x32的交換系統，並以38MHz的時脈運作，整個 系統吞吐量（throughput）可達10Gbits/sec。SBF-VLSI是以single poly double-metal 0.8um的CMOS製程來製作。其設計方式包含全客戶式設計與 合成，整個晶片的面積為11238.1umx12000um，約含有150萬個電晶體。 SBF-VLSI的主要組成元件為多工器（MUX），解多工器（DMX）及共享緩衝 器之主記憶體。MUX/DMX的主要功能為做序列到並行/並行到序列的轉換， 其設計是以雙埠的記憶體和指標器來取代傳統的移位記錄器（shift register）以達到節省面積和降低功率消耗。共享緩衝記憶體是以靜態記 憶體（SRAM）的方式來實現，其輸出電路以再生放大器與內部控制時脈的 方式來達到快速存取與低功率消耗的要求。在CTRL-VLSI的設計方面，我 們討論了各個所需模組的功能，包括共享緩衝器之管理，貯列管理，優先 權控制，多點通訊之支援，流量控制等。以使交換系統在不同的服務品質 （QoS）要求下達到最高的效率。 In this thesis, we design a shared buffer and its controller of an asynchronous transfer mode (ATM) switch. The ATM switch has 32 input ports and 32 output ports, the data rate of each port is up to 155 Mb/s. This switch is a shared buffer switch. It achieves buffer memory utilization improvement through the use of buffer sharing among all output ports of the switch and has a large shared buffer which can save 4096 cells. As a result, this switch can satisfy the cell loss ratio requirements, not only under random traffic conditions but also under burst traffic conditions. Bit-slice techniques are effectively used to realize a high speed switch element as a CMOS VLSI chip set. A unit switch consists of eight shared buffer VLSI's (SBF-VLSI's), and a shared buffer controller VLSI(CTRL-VLSI). Using the VLSI's the 32x32 switch can be mounted on a printed board and operates at 38 MHz. SBF-VLSI is fabricated in single poly double-metal 0.8um CMOS technology and implements a mix of custom and synthesized design approaches. The chip contains 1500k transistors with area 11238.1umx12000um. The main components of SBF-VLSI are buffer memory pool, multiplexer (MUX) and demultiplexer (DMX). A MUX/ DMX with minimum power dissipation and a minimum pattern area are designed using the proposed converter circuits, which use far less registers than traditional serial-to-parallel/parallel- to-serial (SP/PS) conversion circuitry. The buffer memory pool are implemented as on chip SRAM. To minimize power dissipation, the SRAM are partitioned so that only one-eighth will be active each time the SRAM are accessed. The output circuitry of the SRAM is designed to achieve fast access time and low power consumption by using a regenerated sense circuitry. In the high level design of the CTRL-VLSI, we discuss the required functions for every functional block (including buffer management, queue management of cell loss classes and delay priorities, muticast function supporting, traffic control) in detail, study efficient control strategies, and find relative optimal parameters to increase the efficiency of ATM switch under the QoS (Quality of Service) requirements.