CMOS運算放大器之函數測試圖樣產生法

Abstract

本論文中，我們針對ＣＭＯＳ運算放大器提出一函數測試圖樣的產 生法。一個類比電路，其電路行為可用一個數學運算函數表示之，當電路 中有瑕庛存在時，其電路行為將會改變。一個良好的測試圖樣，應該要能 使得正常的與障礙的類比電路有最大的輸出差異。我們針對運算放大器觀 察其在正常運作時與電路中某部分發生障礙時的行為差異，推導出測試圖 樣集。根據推導的論證與電路模擬的驗證，吾人發現所產生的測試圖樣集 可以得到最大的輸出差異，特別是對於電路中輕微的障礙，我們也可以得 到很好的測試效果。最後我們將結果應用到對可程式化增益╱衰減混合訊 號電路產生測試圖樣。 In this thesis, we generate functional test patterns for CMOS operational amplifier. The circuit behavior of an analog circuit can be represented by an arithmetic function. It will deviate from its normal operation when a "fault" exists at the circuit. A good test pattern must give the maximum difference of the output response between the good circuit and the faulty one. We derive a set of functional test patterns based on the analysis to find the maximum difference between the good circuit and the faulty circuit for a CMOS operational amplifier. The theoretical and simulation results show that the derived test patterns do give the maximum difference at the output even when the circuit has a "soft" fault. The results have also been applied to generate test patterns for a programmable gain/loss mixed signal circuit.