視訊壓縮元件之電路設計

Abstract

數位影像和視訊壓縮已經變成愈來愈重要及活躍的領域。壓縮理論、 超大型積體電路技術和編碼標準的進展，使得數位視訊在許多應用中成為 可能的技術。 在本文中，我們提出一種新的影像和 視訊壓縮系統，此系統是根據多維回歸模型所發展出來的。我們利用一個 回歸多項式來描述一群影像資料。我們比較了此系統和傳統JPEG系統的效 能。此系統在低位元率時能提供比JPEG編碼更好的影像品質。我們更針對 編碼器與解碼器其中主要運算部分做了硬體設計。在此硬體設計中，所有 架構完全由加法器所組成，不需要用到乘法器，所以十分適合實作。此系 統中的編碼器將可擁有每秒四億像點的處理速度，而解碼器每秒亦可擁有 四億像點的輸出率。因此，此系統的主要應用將是低位元率即時影像的編 碼與解碼。 Digital image and video compression has become an increasingly important and active field. Progress in compression algorithms, VLSI technology, and coding standards has made digital video an enabling technology for many applications.In the thesis, we propose a new image and video compression system, which is developed based on the multiple regression model. We use a polynomial regression equation to describe a set of image data. We have compared the performance of this system and the traditional JPEG system. This system has better image quality than the JPEG system at low bit rates. We have designed the core operators of the encoder and decoder. In the hardware design, all the architectures are composed of adders, and there is no multiplier in them. So, it is very suitable for VLSI implement. In this system, the operation speed of the encoder is 400M pixels per second and the throughput of the decoder is also 400M pixels per second. So, the potential application is low-bit rate real-time image coding and decoding.