數位行動通訊時序回復及頻率漂移補償器之積體電路設計

Abstract

在數位通訊系統中，接收端需要有正確的時序以對訊號取樣，降低前後資 料之間的干擾。在此我們探討一種時序回復電路，它由時序誤差檢測器、 數位迴路濾波器及數控式振盪器所組成以產生適當的取樣時脈。另外因車 輛移動造成之都卜勒效應以及載波和本地振盪器之頻差會在接收端形成頻 率上的漂移，並使解調之後的訊號產生一固定的相位旋轉量，進而降低系 統的性能。我們應用基頻回授頻率漂移補償技術以改善系統的效能。接收 端亦需能在一連串的資料中，判斷出屬於自己的部份，我們以一個相當簡 單的架構來達到框同步的效果。在本論文中，我們整合了時序回復電路、 頻率漂移補償器及框同步電路，探討其性能表現，並完成超大型積體電路 的設計，經實際製作完成的積體電路晶片測試結果，証明其功能正確無誤 。 In digital communications, correct timing is necessary to reduce the ISI in the receiver. We adopt a timing recovery scheme using the Gardner's timing error detector, a novel digital loop filter and a digital controlled oscillator to generate the optimal sampling clock. The Doppler drift owing to vehicle movement and the frequency difference between local oscillator and carrier will result in a frequency offset in the receiver. The frequency offset will cause a phase rotation in the signal after demodulation and degrade the system performance. A baseband feedback frequency offset compensator is used to improve the performance. In TDMA system, the user's data stream is organized into uniformly-sized groups of bits. For a receiver to detect the incoming data stream, the sampling clock must be synchronized with the data stream's frame structure. We use a simple structure to implement the frame synchronization. In this thesis, timing recovery, frequency offset compensation and frame synchronization are integrated together and implemented by VLSI design using 0.8um silicon process. The total chip size is 3894.2um x 3867.2um. The symbol rate can be at least 3M symbols/ sec.