完整後設資料紀錄
DC 欄位語言
dc.contributor.author魏盟哲en_US
dc.contributor.authorWey, Meng-Jeren_US
dc.contributor.author吳錦川en_US
dc.contributor.authorWu Jiin-Chuanen_US
dc.date.accessioned2014-12-12T02:15:34Z-
dc.date.available2014-12-12T02:15:34Z-
dc.date.issued1995en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT840430054en_US
dc.identifier.urihttp://hdl.handle.net/11536/60655-
dc.description.abstract本論文探討了互補式金氧半超取樣數位至類比轉換器的分析和設計, 主要元件包含 內插器, 和差調變器以及重建濾波器. 內插器將數位 輸入訊號的取樣頻率由 44.1 千赫提高至 11.3 百萬赫. 和差調變器 則採用二階一位元的架構, 將量化誤差所產生的雜訊由原先的平均分佈轉 而向高頻區集 中. 重建濾波器則採用電流式半數位有限脈波響應濾波器, 將和差調變器輸出的數位訊 號轉換成類比輸出訊號, 並濾除掉集中在高 頻的雜訊. 此一數位至類比轉換器以 SPDM 0.8 微米的製程技術作設 計, 以 2800*2800微米平 方的面積完成一個符合十六位元解析度要求的 單一積體電路. This thesis deals with the analysis and design of the CMOS oversamplingDigital-to-Analog converter. The major components in the DAC are interpolator,sigma-delta modulator, and reconstruction filter. The sampling frequency of input digitized signal is raised from 44.1 kHzto 11.3 MHz by the interpolator. The noise which mainly comes from quantizationerror is moved to higher frequency range by the use of second-order single-bitsigma-delta modulator. And the single- bit digital output of the sigma-delta modulator is converted to analog signal by the reconstruction filter which is implemented in current mode semi-digital FIR filter. The noise is filtered outat the same time. This DAC is designed with the SPDM 0.8 um process. It is completely imple-mented in a single chip with active area about 2800*2800 um square. The simula-tion results show the DAC meets the requirement of the 16-bit resolution.zh_TW
dc.language.isozh_TWen_US
dc.subject超取樣zh_TW
dc.subjectoversamplingen_US
dc.title互補式金氧半超取樣數位至類比轉換器之設計與分析zh_TW
dc.titleDesign and analysis of the CMOS oversampling D/A converteren_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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