互補式金氧半積體電路中輸入及輸出緩衝級之新型佈局設計

Abstract

在本篇論文裡提出三種新的佈局方式以應用在積體電路中輸出緩衝級的 設計。由於，當互補式金氧半製程達到次微米領域時，新製程變化如閘極 氧化層變薄，通道變短，LDD結構，源極及汲極之擴散深度變淺以及金屬 矽化物的運用等嚴重地消弱次微米金氧半積體電路之靜電放電保護能力。 欲達到所需之抗靜電能力，用於金氧半積體電路中輸出緩衝電路，本身也 當靜電放電保護元件，必須設計得比長通道元件更大。此外，當金氧半積 體電路之電源供應降下時，為提供足夠之電流驅動能力以推動沉重之輸出 負荷，輸出緩衝電晶體必須設計有較大的通道寬度長度比。這些因素都將 使輸出緩衝電晶體的佈局面積大大增加。為有效縮小佈局面積，我們提出 三種新的佈局方式名為正方環形佈局方式，六角環形佈局方式及八角環形 佈局方式。與傳統用在輸出緩衝級佈局的手指形佈局方式比較，本文提出 的佈局方式能在較小面積上增進輸出電路的電流驅動能力以及P型及 N型 金氧半元件對靜電放電之防護能力。P型及 N型金氧半元件的汲極區面積 及其寄生電容均因採用正方環形佈局方式，六角環形佈局方式或八角環形 佈局方式而有效減小。此特性使所設計的電路更適合於高頻應用。此外， 提出的新型佈局方式也可應用在輸入靜電放電保護電路上。在本文，已針 對各種新型佈局方式實做測試晶片以證明新佈局方式之優於傳統手指形佈 局方式。 In this thesis, we propose three new layout designs of output and input buffers of CMOS IC's. While the CMOS technology has been scaled down into deep-submicron regime with thinner gate oxide, shorter channel length, shallow drain/source junction, LDD (lightly-doped drain) structure, and silicided diffusion, these advanced processes cause serious degradation on the ESD robustness of CMOS IC's. To achieve the required ESD robustness, the output buffer, which also acts as the protection device for the CMOS IC's often has to be designed with much larger dimensions than those in the traditional long-channel CMOS technologies. Besides, when the power supply has been scaled down, the width/length (W/L) ratios of NMOS and PMOS devices in the last stage of an output buffer are must enlarged up to offer enough driving/sinking capability of CMOS output buffer for external heavy loading. All the aforementioned factors will increase the layout area of the output buffer. For this reason, three new layout designs, which include square-type layout, hexagon-type layout, and octagon-type layout, are proposed in this thesis. Comparing to the output buffer by the traditional finger-type layout, the new proposed layout styles can provide the current driving/sinking capability of output buffer and ESD robustness of NMOS (PMOS) of I/O ESD protection circuits within a smaller layout area. The drain diffusion area and parasitic drain capacitance of NMOS or PMOS by this new proposed layout are smaller than those by the finger-type layout. Thus, this proposed layout designs are more suitable for CMOS output buffer in the high-speed applications. Also, they can be used in the input protection circuits to provide the ESD protection for CMOS IC's with smaller layout area. One set of output buffers with different device dimensions and layout spacings have been designed and fabricated by a 0.6-(m SPDM CMOS technology to verify the layout efficiency with comparison to the traditional finger-type layout.