互補式金養半兩級高速類比至數位轉換器之設計與分析

Abstract

本論文描述3伏, 8位元, 50MS/sec的類比至數位轉換器, 主要元件包 含約略比較器(coarse comparator), 精密比較器(fine compa-ator), 數 位修正電路(digital error correction circuit), 時脈產生器(on chip clock generation), 切換開關矩陣電路(switch array circuit). 約略比較器比較輸入電壓與參考電壓的大小,可偵測的最小電壓差為60毫 伏. 精密比較器偵測的最小電壓差為4毫伏,. 數位修正電路根據精密比較 器的比較結果對約略比較器的比較結果做加減1個位元的修正. 此電路共 需10個同步極高的時脈, 故輸入一參考時脈給時脈產生器, 輸出10個時脈 給內部電路用. 約略比較器的比較速度(50M/s)是精密比較器的兩倍(25M/ s),故需兩套精密比較器搭配一套約略比較器,其介面由切換電路來調整. 此類比至數位轉換器以SPDM 0.8微米製程技術來設計,它是工作在-1.5伏 ~1.5伏,參考電壓及輸入電壓限制在-1伏~1伏之間,經過HSPICE模擬符合8 位元解析作度與每秒50百萬取樣,最後將此類比數位轉換器製4995x2815微 米平方的單一積體電路. This thesis describes a 3Volt, 8bits, 50MS/sec A/D converter which is composed of coarse comparators, fine comparators, digital error correction, on chip clock generator, switch array circuit. The coarse comparator can sense 60mV voltage difference and the fine comparators can sense 4mV voltage difference. The digital error correction base on the result of the fine comparator to correct the result of the coarse comparator. The circuit totally need 10 clocks which must synchronize actually. So, we must use a reference clock signal and output 10 clocks for the chip used. The speed of coarse comparators (50MS/s) is twice than the fines (25MS/s). So we use two groups of the fine comparator to meet the speed of the coarse comparators. The role of the interface between the coarse comparators and fine comparators is the switch array. The A/D converter is designed with the SPDM 0.8um process. Its operating voltage is between -1.5v and 1.5v. The reference and input voltage is limited between -1v and 1v. The HSPICE simulation show the ADC have the resolution of 8 bits and the speed of 50MS/s. The A/D converter is completely implemented in a single chip with active area about 4995x2815 micro squares.