架構於加法器陣列之低功率乘法器設計

Abstract

隨著超大型積體電路技術的發展，高速及高密度之晶片製造變得簡而 易行，然而這卻也衍生出功率消耗過大的問題，促使低功率電路之設計變 得日益重要．本篇論文介紹一種以加法器陣列為基本架構之低功率乘法器 的設計方法．我們主要是著重於平衡加法器陣列間的延遲時間，以有效的 減少不必要的訊號轉換．根據這架構所設計出的乘法器不僅可以達到降低 功率消耗的目的，在電路上仍可保持高度之規則性及模組化．最後我們架 構了一個八位元乘法器，以互補式金氧半0.8微米之製程技術並利用功率 估測工具"CB_Power"去估測其實際的功率消耗，結果顯示利用此架構可節 省約24%的功率消耗． As the development of VLSI technology, the high density and high speed chip is easy to implement. The large power dissipation problem, however, is also in company with this development. So the low power circuit design is more and more important. In this thesis, a new design methodology of low power multiplier based on carry-save adder(CSA) array is presented. The proposed architecture is mainly emphasized on the delay- balance of the carry-save adder array to effectively eliminate a large amount of unnecesary transition activities. So in this architecture, the new multiplier can achieve the both high speed and lower power dissipation while maintaning a highly regular and modularized circuitry. Finally, a 8*8 two's complement multiplier is implemented using TSMC CMOS 0.8um technology and estimated by the power estimation tool "CB_Power". The estimation result shows about 24% reduction of the power dissipation by the proposed architecture.