可程式化寬頻除頻器模組

Abstract

信號產生器為達到好的相位雜訊(Phase noise),﹞@般皆以產生高頻信號 ，而後加以降頻而得到全頻率的信號．在這裡我們完成一除頻器模組，並 且產生一640MHz本地振盪器信號提供給混波器以產生100KHz~160MHz 信 號. 主頻率640~1280MHz經過模組後且加以程式控制便產生全頻率信號且 向位雜訊可達-130dBc/Hz(10KHz). 其中將設計數個串接除頻器, HighQ 濾波器, 及控制用的開關, 寬頻放大器,混波器, 頻率倍頻器, 壓控 振盪 器及頻率合成器. 在除頻器模組中, 我們設計量測了UPB581, UPB584, UPB565; GEC Plessey之SP8605,在相位雜訊, 輸出功率上比較其結果, 作 為我們主要除頻元件. 對濾波器而言, 設計低通濾波器參考Elliptical型 式設計,使Stop Band 皆小於-40dB,如此能使由除頻器之諧波消除. 帶通 濾波器則希望頻寬盡量小. 開關由於整體電路, 我們設計了SPDT, SP3T. 在SPDT上設計了4 種型式的架構並比較其在損失, 隔離度之響應. 使隔離 度在1.28GHz能有-30dB以上. 使開關能有效隔離信號, 對後接電路不造成 影響. 放大器則希望在160~640MHz頻寬中能有10dB增益且S11, S22皆小 於-15dB,使輸入和輸出端能匹配產生最大功率傳遞.提供一640MHz本地振 盪器我們設計兩種方法. 第一種使用40MHz倍頻4次得到7dBm功率輸出. 相 位雜訊達到-104dBc/Hz(10KHz offset). 第二種以共射極形成共振電路而 振盪.輸出功率得到7.5dBm,相位雜訊-104dBc/Hz(10KHz offset). In this thesis we design a wideband, lower phase noise frequency dividermodule that phase noise is as low as -130dBc/Hz(offset 10KHz)and generate a 640MHz local oscillator to support mixer generating100KHz~160MHz. Frequency is covered from 100KHz extend to 1280MHz.Module include some frequency divider, high Q filters, control switches,wideband amplifiers, frequency doublers, voltage control oscillator(VCO).After finishing all component's design and test, we try to integrate itand generate a high performance, high Q signal. In frequency divider module, we test NEC compant's UPB581, UPB584, UPB565, GEC Plessey's SP8605 frequency dividers and compare its phase noise and output power. We design and compare elliptical and chebyshevfonts low pass filters(LPF) in the high frequency's response. LPF willisolate signal 40dBc in the stop band and pass signal in the pass band.Design a narrow bandwidth band pass filter(BPF) to reject the unwanted signal. Design single pole double throw(SPDT) and SP3T switch. We compare4 style SPDT's loss and isolation then choose the best one to our controlcomponent. We design a 10dB gain, matched 160~640MHz wideband amplifier to compensate system gain and a high gain, matched 640MHz amplifier to driver local oscillator 640MHz to 7 dBm. To generate 640MHz oscillator, we use two methods to achieve it.One use a stable, precision 40MHz multiplier 4 times and cascade BPFto reject high order harmonics and fundamental signal to get 640MHz.In this method, we design a module that power is 7dBm, phase noise is-104dB(10KHz offset). In another method, we design a common Emitter VCO and program synthesizer to generate a high Q, low phase noise640MHz oscillator. For this method, we also design a module that power is 7.5dBm, phase noise is -104 dBc/Hz(10KHz offset).