AAL Type 1 晶片設計

Abstract

ATM網路卡的製作方興未艾，其目的就是在小型系統測試ATM技術的成熟度 。以製成網路卡為目標的AAL Type 1 晶片，可完成一些ATM層和AAL層的 功能，包括封包組合(Cell Assembly)、 封包分解(Cell Disassembly)以 及在電路模擬(Circuit Emulation)的同時所使用的同步餘時戳記法( Synchronous Residual Time Stamp；SRTS)。所花費的種種心思和努力就 是希望在定位元傳輸率(Constant Bit Rate；CBR)傳送資料的同時，也能 讓通訊雙方知道彼此的時序訊息，以作為回復時序所用；本論文利用 Xilinx這家公司為FPGA(Field Programmable Gate Array)所出的電腦輔 助設計應用軟體來設計電路，所得時序圖亦為其模擬結果。透過電話線所 傳送的資料型態必將成為將來寬頻整合服務數位網路(BISDN)之重要環節 ，由此可窺見AAL Type 1晶片的設計和製作是有其發展的必要性。 In order to experiment the ATM technology in a subsystem, implementation of the Network Interface Card (NIC) has been actively executed. We have conducted the AAL type 1(AAL 1) chip design for NIC. The chip performs ATM layer and AAL 1 functions such as cell assembly, cell disassembly, Synchronous Residual Time Stamp(SRTS) for circuit emulation. The intend of these development efforts isto transfer service data units with a constant bit rate and timing information between source and destination. In the thesis, we use Xilinx Viewlogic to process our design for circuits and simulation. While the transport of currently exsitingxisting circuit-based signals is believed to be an important feature of B-ISDN,it isnecessary to design and implement an AAL 1 chip.