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dc.contributor.author趙豊昌en_US
dc.contributor.authorChao, Lee-Changen_US
dc.contributor.author唐麗英, 李威儀en_US
dc.contributor.authorLee-Ing Tong, Wei-I Leeen_US
dc.date.accessioned2014-12-12T02:16:48Z-
dc.date.available2014-12-12T02:16:48Z-
dc.date.issued1996en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT850031014en_US
dc.identifier.urihttp://hdl.handle.net/11536/61454-
dc.description.abstract在積體電路製造上,隨著晶圓面積的增大﹐缺陷出現群聚現象﹐卜瓦松良 率模式會因低估良率而不再適用。而負二項良率模式中的缺陷群聚參數與 晶片面積有關﹐同時也可能由於抽樣限制造成值群聚參數逐批不同﹐這都 造成負二項模式在良率分析上的不便。至於其他的複合卜瓦松良率模式則 大都只考慮到晶片面積與產品良率間的關係﹐而忽略了產品的製程複雜度 對良率的影響。為了能夠再度擁有卜瓦松良率模式既簡單又精確的特性。 本研究於是利用類神經網路的技術對晶圓上的缺陷數目做一修正﹐以消除 缺陷群聚現象對卜瓦松良率模式的影響。如此便可利用修正過的卜瓦松良 率模式來預測及分析良率。本研究最後以一實例來驗證本研究所提之修正 卜瓦松模式之良率預測的效果,確實比其他良率模式為佳。 In integrated circuit (IC) manufacturing, a wafer's defects tend to cluster. As the wafer size increases, the clustering phenomenon of the defects becomes increasingly apparent.When the conventional Poisson yield model is used, the clustered defects frequently cause false results. In this study, we propose a neural network-based modified Poisson yield model to predict the wafer yield in IC manufacturing. The proposed approach can reduce the phenomenon of the false predictions caused by the clustered defects. A case study is also presented, demonstrating the effectiveness of the proposed approach.Keywords: integrated circuit, defects, cluster, yield model, neural networkzh_TW
dc.language.isozh_TWen_US
dc.subject積體電路zh_TW
dc.subject缺陷zh_TW
dc.subject群聚zh_TW
dc.subject良率模式zh_TW
dc.subject類神經網路zh_TW
dc.subjectintegrated circuiten_US
dc.subjectdefectsen_US
dc.subjectclusteren_US
dc.subjectyield modelen_US
dc.subjectnerual networken_US
dc.title利用類神經網路構建之積體電路良率預估模式zh_TW
dc.titleThe Yield Prediction Model with Neural Network for Integrated Circuit --- Based on Poisson Modelen_US
dc.typeThesisen_US
dc.contributor.department工業工程與管理學系zh_TW
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