半導體晶圓廠黃光區即時派工策略之構建

Abstract

半導體為目前國內最熱門也是最高科技的產業之一，近年來其產值帶動著 國內整體產業的發展。晶圓製造廠和其他零工型生產最大的不同是晶圓生 產有再回流性質，導致整個流程複雜混亂且不易控制。再加上機台的不穩 定當機、廠內的緊急訂單等特性使得目前文獻中所針對零工型生產探討的 派工法則並不完全適於晶圓製造廠。實際上黃光區就整個晶圓廠而言可謂 為物流配送中心且經常為瓶頸所在。故本論文首先即針對晶圓製造廠物流 中心－黃光區，分析影響其派工的所有因素，本派工演算法考慮了維修保 養、緊急批、等候時限、光罩置換、在製品量控制和交期進度。然後構建 一黃光區派工演算法－DPPA及對應之投料法則，在本演算法中採用MIVS及 RTR方法來達成顧客交貨水準及生產線平衡之目的。本研究以C語言為模擬 驗證工具，利用Duncan作統計檢定，探討DPPA和FIFO、SPT、SRPT、EDD、 CR在各項指標上之績效比較。模結果顯示DPPA在達交率、線性產出、在製 品分佈、週期變異數、週期平均數及在製品量方面均較其他派工法則有較 佳表現。關鍵字：晶圓製造、黃光區、派工法則、交貨水準、生產線平衡 Semiconductor industry is one of the booming industries in Taiwan in these two decades. Wafer fabrication owns the most complicated process in semiconductor manufacturing. The photolithography area is in practice treated as the control center of wafer flows. Developing a comprehensive dispatching rule for this area to improve its performance as well as the performance of the entire fab is important. This study first investigates all factors which affect the system performance as well as the corresponding dispatching algorithm in photolithography area. DPPA (Dispatching Procedure for Photolithography Area) is then developed with the consideration of preventative maintenance, hot lot, queue time limit, restriction of mask, WIP control, and due date control. Method, MIVS and RTR, to enhance line balance and on-time delivery are also employed in DPPA. A release policy corresponding to the proposed dispatching procedure is also designed. A fab simulation model written in C and real world fab data are employed to experiment the effectiveness of DPPA. Five conventional dispatching rules, FIFO, SPT, SRPT, EDD and CR, are used to be compared with. Results demonstrate that DPPA shows superiority on the performance measures of on-time delivery, mean tardiness, linear output, WIP distribution, mean cycle time and queue time, standard deviation of cycle time, number of reworks, and total WIP. Results also conclude that comparing with other conventional dispatching rules, DPPA yields shorter cycle time and lower WIP level while resulting in an equal throughput level. Keyword : wafer fabrication, photolithography area, dispatching rule, on-time delivery, line balance.