Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 趙英宏 | en_US |
dc.contributor.author | Chao, Ying-Hung | en_US |
dc.contributor.author | 唐佩忠 | en_US |
dc.contributor.author | Tang Pei-Chong | en_US |
dc.date.accessioned | 2014-12-12T02:17:08Z | - |
dc.date.available | 2014-12-12T02:17:08Z | - |
dc.date.issued | 1996 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#NT850327037 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/61693 | - |
dc.description.abstract | 在伺服控制系統之中,最內層的電流控制回路的頻率響應要求相當高,因 此,以往都是以類比式的磁滯控制等方式來達成其高頻寬的要求, 不過 ,由於類比電路的參數調整不易,而且容易受到環境中的雜訊干擾,所以 實非最佳選擇。 而本論文將採用數位方式 來實現電流控制回路,而一般來說可分為DSP 或是硬體數位電路的方式來 實現之,不過,由於DSP速度對電流控制回 路來說仍嫌不夠,因此,我們 決定以硬體數位電路的方式來實現之。我們的最終目標是完成一個以ASIC 方式設計之電流控制晶片,不過,首先,我們採用了FPGA做為設計ASIC前 的基礎及預備工作,來進行電流控制晶片的設計,並且在這個階段對電路 進行細部的修改,以確認出電流控制晶片的內部電路,接著,我們探討了 FPGA的諸多特性,諸如啟動程序、重置程序等;並明確的針對FPGA的電氣 特性來規畫ASIC的規格。以避免在未來我們將FPGA中設計的電路轉換為 ASIC設計時,因為規格不合而產生晶片不能正確工作的人為錯誤。 最後,雖然完成了數位式三相電流控制晶片的ASIC設計,並完成了所需的 每一項後段的驗證工作,但因為不能實地將其製作出來,因此我們只能由 其模擬結果得知,ASIC設計出來的電路和FPGA設計出來的電路有著一樣好 的表現。 In the Servo Control System, the frequency response of the inmost currentcontrol loop is very high. So, in the original design, some analog implementation,like hysteresis control, is used to achieve the requirement of high frequency response. Because the parameters of analog circuits is hard to adjust, and is easily disturbed by the environment noise. So, it's not the best choice. In this paper, we use digital way to implement current control loop, andgenerally speaking, we have two choices, one is DSP, the other is to use digital circuit. But to control the current loop, DSP seems not to be fast enough. So we decide to use the digital Circuit to do this. Our final goal is to have a current chip designed by the ASIC way. Before we begin the ASIC Design, the FPGA design is used to be the base of ASIC Design. We did detail circuit design in the FPGA, first. Change and verify the internal circuit of our current chip when needed. Then we study the features of the FPGA, like startup procedure, reset procedure etc., and clearly plan the detail electronic characteristic of our ASIC Design to avoid the mismatch of the specification between FPGA and ASIC Design. Finally, although we have done the ASIC design of three phase current control chip, and finished every verification step of the IC Design. But we can't get the CHIP to test it on line,so we are just able to check the simulation result to know that the ASIC performance is equal or even higher than FPGA Design. | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.subject | 電流控制 | zh_TW |
dc.subject | 晶片 | zh_TW |
dc.subject | Current Control | en_US |
dc.subject | Chip | en_US |
dc.title | 數位式三相電流控制晶片之研製 | zh_TW |
dc.title | Design and Implementation of an Three-Phase Current Control Chip | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電控工程研究所 | zh_TW |
Appears in Collections: | Thesis |