標題: 金氧半電晶體內界面缺陷所產生汲極漏電流的溫度效應
Temperature Effect on Interface Trap Induced Drain Leakage Current in n-MOSFET's
作者: 劉家瑋
Liu, Chia-Wei
汪大暉
Wang Tahui
電子研究所
關鍵字: 順序穿隧;能帶-能帶穿隧;界面缺陷;熱能激發;電場激發;sequential tunneling;band-to-band tunneling;interface trap;thermionic emission;field emission
公開日期: 1996
摘要: 在金氧半場效電晶體中,熱載子加壓所產生的界面缺陷可引起額 外的汲極漏電流已被廣泛的討論。在以前,這種現象被歸於與缺陷有關的 電場效應,例如,缺陷所引發的順序穿隧電流或由於氧化層電荷累積造成能 帶-能帶穿隧電流的增加。除了電場的效應之外,在最近的實驗中亦發現由 缺陷所造成的汲極漏電流,在某些偏壓條件下與溫度有相當密切的關係。 當溫度升高時,這種漏電流會變的很嚴重,甚至影響到動態存取記憶體的更 新時間。 在本篇論文中,我們量測和模擬n型金氧半場效電晶體中 界面缺陷所造成汲極漏電流的溫度效應。為了評估溫度效應,我們採用完 整的能帶-缺陷-能帶的漏電機制去模擬量測的汲極漏電流.在這個模擬中, Si/SiO2界面的漏電路徑由電洞從界面缺陷激發到共價鍵和電子從界面缺 陷激發到導電帶而形成,電洞和電子的激發皆可經由電場或熱能的激發來 達成。在實驗中,我們用傳統的源汲/汲極n型金氧半場效電晶體施以最大 基極入射電流加壓。在此加壓條件下,大量的界面缺陷會被產生而且氧化 層電荷所造成的電場變化非常小。結果顯示出在不同的偏壓條件下,汲極 漏電流的與溫度有不同的相依關係。根據我們的模擬,當溫度升高時,在較 低的汲極-源極偏壓下所產生大量的額外汲極漏電流是由於熱能激發所造 成,然而在較高的汲極-源極偏壓下所產生的微量增加的汲極漏電流是由矽 能帶變窄所造成。 It was reported that hot carrier stress generated interface traps can introduce anadditional drain leakage current in an off-state MOSFET. Previously, this phenomenonwas attributed to the trap-related field effects such as trap- assisted sequential tunnelingor enchancement of band-to-band tunneling due to the trapped charge build-up. Inadditional to the field effects, recent experimental result showed that the trap-induceddrain leakage exhibits a strong dependence on temperature at certain applied biases. Thisleakage current becomes much aggravated as the temperature increases and thus may haveimpact on a DRAM refresh time. In this thesis, temperature effect on interface trap induced drain leakage current hasbeen characterized and modeled in off-state n-MOSFET' s. To evaluate the temperature effect,we adopted a complete band-trap-band leakage model to reproduce the measured drain leakagecurrents. In this model, the leakage path at the Si/SiO2 interface is formed by holeemission from interface traps to a valence band and electron emission from the trapsto a conduction band. Both hole emission and electron emission can be carried out via fieldemission or thermionic emission. In measurement, a conventional S/D n-MOSFET was used.The device was subject to maximum substrate current stress. Under the stress condition,a large amount of interface traps were created and the trapped charge induced interfacefield variation is small. The result reveals that the drain leakage current exhibitsdifferent temperature dependences in different bias regions. According to our trap-assistedleakage model, as the temperature rises, the greatly increased drain leakage current at alow drain-to-gate bias is caused by enhanced thermionic emission while the slightlyincreased drain leakage current at a large drain-to-gate bias is due to the Si energybandgap narrowing.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT850428021
http://hdl.handle.net/11536/61885
顯示於類別:畢業論文