用於SRAM設計之雜訊消除法

Abstract

在這篇論文中,提出了兩個描述SRAM雜訊的模型,其一是針對輸 出端的雜訊模型,另一為SRAM內部所引發的對地雜訊.根據這兩個雜訊模 型,可以輕易地用筆算出所需求的輸出元件大小,以符合對雜訊與速度上的 要求,因為通常速度越快雜訊也越大. 利用這兩個模型, 再發展逋減小雜 訊的方法, 在輸出雜訊減小方面有兩個方法, 而對地雜訊則有四種方法. 本文也針對這些方法作了討論與比較. 這兩個模型經模擬驗證,前者誤差 小於10%, 可謂一精確快速的手算模型, 而後者的誤差則為50%, 但卻可題 示改進的方向,可謂具物理意義的模型! In general, for SRAM design, the key design features are small chip size, high speed and low power concern. But all these performances must be based on low noise disturbance. Once the noise induced the chip to be fail,all the high performance issues described above will become meaningless.There are two methods to get low noise disturbance environment. One is tocreate a good noise immunity circuit to avoid outside noise. The other isto create a low noise source circuit to reduce inner disturbance which isproposed in this work. The noise source of chip is always causedby outputbuffer. Output buffer will induce I/O and ground noise bounce. We derivedtwo new manipulative technologies for noise bounce calculation. The first,N - separate resistance, is to estimate I/O noise bounce. It can decidethe output buffer size and the speed of output buffers simultaneously.The second, with a simple physical concept, Q = CV = IT,we can estimatephysically the noise ground bounce, owing to the inductance. Using thesemethods, we may get the output buffer size precisely. And thus a low noiseoutput buffer can be derived.