完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 曾華洲 | en_US |
dc.contributor.author | Tseng, Hua-Chou | en_US |
dc.contributor.author | 張俊彥 | en_US |
dc.contributor.author | Chun-Yen Chang | en_US |
dc.date.accessioned | 2014-12-12T02:17:26Z | - |
dc.date.available | 2014-12-12T02:17:26Z | - |
dc.date.issued | 1996 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#NT850428026 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/61892 | - |
dc.description.abstract | 在本論文中,超高真空化學分子磊晶(ultrahigh vacuum- chemical molecular epitaxy, UHV-CME)系統首先被裝設完成,以進行 低溫矽選擇性磊晶成長(selective epitaxial growth, SEG)及氣相源 摻雜(gas source doping, GSD)在極大型積體(ultra-large-scale- integration, ULSI)電路中超淺接面應用之研究。 矽選擇性磊 晶成長需要三個主要步驟:分別為隔絕材料的沉積、以蝕刻方式定義出磊 晶視窗、在基板上磊晶成長。磊晶層的品質嚴重受晶片準備和沉積狀況的 影響。在本文的討論中,發展一種低熱預算的非即時熱清洗方法以去除乾 式蝕刻引起的缺陷和降低表面殘留物;示範一種新奇的隔絕氧化層結構以 大大地減低在即時熱清洗製程中所造成的氧化層凹陷的形成;以及藉由改 變不同的隔絕材料來控制刻面(Facet)的方向,以上三點是本文中要探討 的主題。因為這三個主題也是阻礙矽選擇性磊晶成長廣泛應用的因素。 一種低熱預算的非即時清洗方法已經被提出。我們探討矽晶層選擇性成長 在經過反應離子蝕刻(reactive ion etching, RIE)的矽基板上所發生的 問題,所使用的蝕刻氣體為CF4,CHF3和Ar。來自於反應離子蝕刻所引起 的缺陷和污染會造成不平整的磊晶層表面並且會減損電流-電壓的特性。 而且在磊晶層和經過反應離子蝕刻過的基板之介面上會有碳化物層的出現 。使用一種有效又方便的蝕刻後處理(after-etching treatment, AET)方 法,即是利用一種CF4/O2的低能量電漿處理,我們便能夠在有圖形的氧化 層視窗中,得到一個乾淨的矽晶表面以提供選擇性磊晶成長之用。 我們也提出三種隔絕氧化層的結構來研究此三種結構在即時熱清洗過程中 對於氧化層凹陷形成的對抗能力。相較於濕式氧化層及TEOS氧化層,N2O 退火的氧化層╱TEOS氧化層此種堆疊結構有最好的對抗氧化層凹陷的能力 ,並且也有最好的電性表現。這是由於此種堆疊結構在隔絕氧化層和矽基 板間有較小的介面應力存在的緣故。對於N+-P選擇性磊晶成長的二極體而 言,側壁上的傷害是破壞電流-電壓特性的最主要因素。我們也提出另一 種方法,那是結合快速氫氟酸浸泡和低溫的熱清洗步驟,經過選擇性磊晶 成長之後,N+-P選擇性磊晶成長的二極體,不但沒有氧化層凹陷的 對於不同的隔絕材料在低溫選擇性磊晶成長對於刻面(Facet)形成的影響 也是我們討論的項目。我們討論的隔絕材料包含氮化矽層,濕式氧化層, TEOS氧化層。當使用TEOS氧化層時,我們首先成功地成長出沒有刻面,沒 有雙缺陷(Twin)的選擇性成長的磊晶層。我們並且提出一種模型來解釋對 於不同的隔絕材料而言,會有各自偏好的刻面(Facet)方向。那是由於對 不同的隔絕材料而言,在矽晶層和隔絕材料之間有不同的介面自由能,因 此,才會有不同偏好的刻面方向。根據這個模型,我們知道在氮化矽層, 刻面方向為<111>;在濕式氧化層,刻面方向為<311>;在TEOS氧化 氣相源摻雜是具有:少晶格缺陷、淺接面形成、高摻雜濃度的一種選擇性 摻雜方法。在氣相源滲雜的過程中,藉由雙硼化氫(Diborane)的熱分解而 產生的硼原子,將會擴散到矽晶格中以形成一摻雜層,而且可能會和矽基 板反應形成一矽化硼層。我們並且討論了在不同摻雜條件下氣相源摻雜層 的特性,並且討論了藉由氣相源摻雜法形成的P+-N二極體的電流-電壓特 性。 利用1%雙硼化氫稀釋在氫氣當中,以此作為反應氣體來沈積 矽化硼層。我們使用原子力顯微鏡(AFM),歐傑電子分析儀(AES),來分析 此矽化硼層的特性。利用二次離子質量分析儀(SIMS),來決定界面的深度 。在可見的晶核形成之前,有效的摻雜過程已經完成。當通入小劑量的雙 硼化氫時,小顆粒會在矽基板表面形成,而且當通入較大劑量雙硼化氫時 ,顆粒會逐漸聚集而形成不平整的表面。當成長溫度高於800℃時,根據 歐傑電子分析儀(AES)的縱深分析,此矽化硼層的組成為SiB6。在不同實 驗條件之下,我們討論接面深度和片電阻間之關係。我們並且進行沈積後 快速熱 最後,我們使用1%和0.1%雙硼化氫稀釋在氫氣中作為反應 氣體來進行氣相源摻雜之研究。我們利用原子力顯微鏡(AFM),二次離子 質量分析儀(SIMS),和四點探針來研究不同反應氣體濃度在表面平整度、 摻雜分佈和片電阻的影響。我們並且利用氣相源摻雜法,在不同摻雜條件 下,製作P+-N二極體,以研究此二極體的電流-電壓特性。選擇適當的反 應氣體濃度(0.1%),我們便能得到平滑的矽表面,超淺的接面深度,淺 達35 nm,以及高達1020 cm-3的表面濃度。而且,製作擁有優異電流-電 壓特性的P+-N二極體,它具有0.151 nA/cm2的面漏電流密度和3.95 pA/cm 的周圍□ 漏電流密度。 A cold-wall ultrahigh vacuum-chemical molecular epitaxy (UHV-CME) system has been installed to perform low temperature Si selective epitaxial growth (SEG) and gas source doping (GSD) for ultrashallow junction formation in ultra-large -scale- integration (ULSI). The Si SEG requires three main steps, isolation material deposition, etching to define epitaxial windows, and epitaxial growth on the substrate. The quality of the SEG epilayers is highly influenced by wafer preparation and deposition conditions. Developing a low thermal budget ex situ cleaning method to remove the dry etching damage and reduce the surface residuals, demonstrating a novel isolation oxide structure to largely eliminate undercut formation during in situ thermal cleaning process, and In chapter 3, a low thermal budget ex situ cleaning method has been reported. The epitaxial silicon layer selectively grown on the reactive ion etched (RIE) silicon substrate using CF4, CHF3, and Ar etching gases has been studied. Defects and contaminants induced by the RIE process result in a rough epilayer, and degrade the current-voltage (I- V) characteristics. An interfacial carbide layer is present between the epilayer and the RIE treated substrate. Using an efficient and convenient after-et Three isolation oxide structures have been prepared to study their resistance to the undercut formation during in situ thermal cleaning process. The N2O annealed oxide/TEOS oxide stacked structure has the best resistance to the undercut formation and exhibits the best electrical characteristics compared to the other two isolation oxide structures prepared in the study, which are a wet oxide and a TEOS oxide. This is ascribed to a smaller interfacial stress between the isolation oxide and the sili Effects of isolation materials on facet formation for low temperature Si SEG have been demonstrated in chapter 4. The activation energy of the Si epitaxial growth is 47.35 Kcal/mol which corresponds to the activation energy of hydrogen desorption from the Si (001) surface. The isolation material includes silicon nitride, wet oxide, and TEOS oxide. Using a TEOS oxide mask, for the first time, we obtain a low temperature Si SEG layer without facets and twins formation. Therefore, we have proposed The isolation material includes wet oxide, TEOS oxide, and silicon nitride. Using a TEOS oxide mask, we first obtain a low temperature Si SEG layer without facets and twins formation. We also propose a model to explain the preferred facet plane orientations for different isolation materials. Due to the different interface free energies between the Si layer and the isolation material, distinct favored facet planes can be obtained for different isolation materials. GSD is a selective doping method with little crystallographic defect, shallow junction depth, and high doping concentration. During GSD process, boron atoms produced from pyrolysis of diborane diffuse into the Si lattice to form a doping layer, and may react with the Si substrate to form a boron silicide layer. Characterizations of the GSD doping layer and I-V characteristics of P+-N diodes formed by GSD method have been discussed with different doping conditions. A boron containing layer deposited by using 1 % B2H6 diluted with H2. The deposited layer were characterized by atomic force microscope (AFM) and Auger electron spectroscopy (AES), and the junction depth was determined by secondary ion mass spectroscopy (SIMS). Effective doping is accomplished before perceivable nucleation is initiated. Islands are first formed on the substrate surface at a small dose of diborane, and the grains coalesce to form a rough film for higher doses. At growth temperatu Deposition and reaction of boron with Si surface by flowing high concetration (1%) and low concentration (0.1%) of B2H6/H2 gas mixtures onto the Si substrate at high temperature of 805 ℃ are studied. Atomic force microscopy (AFM), secondary ion mass microscopy (SIMS), and four point probe were used to study the influences of the gas mixture concentrations on the surface morphology, doping profile, and sheet resistance, respectively. The former (1%) forms a boron silicide layer on Si surface while | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.subject | 超高真空化學分子磊晶系統 | zh_TW |
dc.subject | 選擇性磊晶成長 | zh_TW |
dc.subject | 氣相源摻雜 | zh_TW |
dc.subject | 極大型積體電路 | zh_TW |
dc.subject | 超淺接面形成 | zh_TW |
dc.subject | Ultrahigh Vacuum-Chemical Molecular Epitaxy System | en_US |
dc.subject | Selective Epitaxial Growth | en_US |
dc.subject | gas source doping | en_US |
dc.subject | ultra-large -scale-integration circuit | en_US |
dc.subject | ultra-shallow junction formation | en_US |
dc.title | 利用超高真空化學分子磊晶系統進行低溫矽選擇性磊晶成長及氣相源摻雜之研究 | zh_TW |
dc.title | Studies of Low Temperature Silicon Selective Epitaxial Growth and Gas Source Doping by Ultrahigh Vacuum-Chemical Molecular Epitaxy System | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
顯示於類別: | 畢業論文 |