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dc.contributor.author沈冠岳en_US
dc.contributor.authorShen, Kuan-Yuehen_US
dc.contributor.author汪大暉en_US
dc.contributor.authorTahui Wangen_US
dc.date.accessioned2014-12-12T02:17:27Z-
dc.date.available2014-12-12T02:17:27Z-
dc.date.issued1996en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT850428033en_US
dc.identifier.urihttp://hdl.handle.net/11536/61899-
dc.description.abstract本論文中,我們量測並模擬電子穿越薄氧化層(<5nm)的現象。我們的 模式考慮了兩種主要的物理機制-電子的量子干涉和表面能階的量子化。 此外,相關研究指出在加壓過的氧化層中,氧化層缺陷的產生會導致額外 的漏電流。這種微量的漏電流對快閃式記憶體裝置的可靠度有劇烈的影響 ,在本論文中我們予以探討。 最近的研究顯示,3nm到6nm厚的薄氧化 層之電流電壓曲線呈現振盪現象。令人迷惑的是,這種現象在較厚(>8nm) 或特別薄(<2nm)的氧化層中反而看不到。此現象背後的物理機制據信源於 二氧化矽導帶中電子的量子干涉。吾人藉由一適切的模式以量化此量子干 涉造成之振盪部份,則諸如氧化層電場、氧化層厚度、電子在氧化層導帶 上的等效質量均可由量測電流電壓曲線的振盪峰值和週期萃取出。 除 了電子的量子干涉效應,在強大電場下矽基座表面的電子能階也會出現量 子化的效應。此表面能階量子化的效應在電荷穿越薄氧化層的現象中也佔 有很重要的地位。在我們的模式中,電子束縛在p型矽反轉層而被視為受 陷電子。我們由此觀點發展此受陷電子穿越至二氧化矽導帶的傳輸模式。 最後,加壓造成的氧化層漏電流在最近幾年廣受矚目。我們在理論方面, 推導了電子經由氧化層缺陷之序列穿隧模式。此模式同時包含電子的量子 干涉和表面能階量子化效應,而實驗的結果和我們模式的推算吻合。 In this thesis, the electron transport across thin oxide films (<5nm) was characterized and modeled. Two major physical phenomena, electron-wave quantum interference and surface quantization, were taken into account in our model. Furthermore, it was reported that oxide trap creation in stressed oxide can introduce an additional leakage current. This low-level leakage may have great impact on the reliability of flash EEPROM devices and was investigated in this work. Recent studies showed that the I-V characteristics in thin oxide films from about 3nm to 6nm exhibits an oscillatory feature. This intriguing feature is apparently not observed in thicker oxides (>8nm) or in extremely thin oxides (<2nm). The physical mechanism behind this phenomenon is belived due to quantum interference of electron wave within the SiO2 conduction band. By developing an appropriate model to quantify the oscillation component, oxide parameters such as oxide field, oxide thickness and effective electron mass in SiO2 conduction band can be extracted by measuring the peaks and the period of the oscillation in the I-V characteristics. In addition to quantum interference effect, surface quantization in Si substrate is expected to appear at a large field. The surface quantization may also play a significant role in charge transport across thin oxide. In our model, the surface electrons are bounded in p-type Si inversion layer and are treated as trapped electrons. A transport model for electron from trap states to the SiO2 conduction band was developed here. Finally, stress-induced leakage current (SILC) has drawn much attention recent years. In the theoretical respect, we develop a model for electron sequential tunneling via trap states in oxide. Both quantum interference and surface quantization effects are included in the model. Agreement between the measured calculated results is obtained.zh_TW
dc.language.isozh_TWen_US
dc.subject量子干涉zh_TW
dc.subject表面能階量子化zh_TW
dc.subject加壓造成的氧化層漏電流zh_TW
dc.subjectquantum interferenceen_US
dc.subjectsurface quantizationen_US
dc.subjectstress-induced low-level leakage currenten_US
dc.title薄氧化層的金氧半元件中閘極漏電流之模式zh_TW
dc.titleModeling of Gate Leakage Current in Thin Oxide n-MOS Devicesen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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