標題: | 氧化鉭在超薄疊層介電質之應用與以電漿退火降低漏電流之研究 Study of Ta2O5 as Ultra-Thin Stacked Gate Material and Leakage Current Reduction by Plasma Annealing |
作者: | 黃以理 Huang, Yi-Lee 孫喜眾 Shi-Chung Sun 電子研究所 |
關鍵字: | 氧化鉭;疊層介電質;N2O氮氧化層;電漿退火;Ta2O5;Stacked dielectric;N2O-grown oxynitride;Plasma annealing |
公開日期: | 1996 |
摘要: | 先前的研究指出,化學氣相沈積二氧化矽/熱二氧化矽的疊層介電質作為 金氧半元件的閘極材料具有可以避免製程所引發的缺陷之優點。本論文將 探討氧化鉭/熱二氧化矽疊層介電質結構。氧化鉭的使用著眼於其高介電 常數,而應N2O氮氧化層則是因為氮會結合於二氧化矽/矽的界面上使元件 有較高的可靠性。我們針對電流-電壓、電容-電壓特性以及可靠性、傳導 機制等方面做研究,並進一步實做出金氧半電晶體,來和以單層二氧化矽 或氧化鉭/O2成長熱二氧化矽為閘極介電層之元件做比較。 低溫 電漿退火在降低化學氣相沈積氧化鉭漏電流的應用也將在本論文做一研究 。各種參數的影響如氣氛、壓力、功率和下電極材料的影響將被探討。我 們發現利用低壓N2O氣氛的環境退火有助於降低漏電流,但會對電容特性 有不良的影響。 Previous study used CVD oxide/thermal SiO2 stacked dielectric for MOS gate material with the advantages of high resistance to process induced defect density. Ta2O5/thermal SiO2 stacked gate dielectrics have been explored in this thesis. Ta2O5 was used because of its high dielectric constant and N2O-grown oxide was used due to the nitrogen incorporation in the SiO2/Si interface which leads to a high device reliability. The current-voltage, capacitance-voltage characteristics have been investigated as wellLow-temperature plasma annealing was investigated to reduce the CVD Ta2O5 leakage current. The effect of ambient, pressure, power, and bottom electrode were examined. It was found that annealing in low pressure and in N2O are effective in reducing leakage current but will degrade the capacitance performance. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT850428074 http://hdl.handle.net/11536/61944 |
Appears in Collections: | Thesis |