IS-54無線通信標準之數位接收器製作

Abstract

在本篇論文中, 我們研究北美數位蜂巢式行動通訊系統之接收器的兩個 項目: 一是等化器的積體電路設計, 一是相關碼的解碼方法. 我們應用 多重訓練雙向式最小均方法與分量間寬之決策回授結構至等化器中. 並提 出含階層式狀態轉換控制器的定製型可程式化架構來實現它. 模擬顯示, 在車速每小時80公里下, 提出的等化器可有低於 2.996% 下的錯誤率效 果. 此外, 我們也用FPGA來製作它. 硬體可以以 1.5552 百萬赫茲的操作 頻率, 在1.38的資料槽時間完成工作, 並只使用2765.5的邏輯單元. 而 在相關碼的解碼上, 我們提出雙向式 Viterbi演算法和雙向式無尾式演算 法. 使用雙向式的解碼, 可降低資料槽中帶狀雜訊的干擾. 模擬顯示, 提 出的雙向式演算法比單向式演算法有更佳的錯誤更正能力, 並在車速每小 時80公里下, 有低於 1.36% 的錯誤率效果. In this thesis, two important issues in the digital recevier of the IS-54specifications for the North American Digital Cellular (NADC) mobilephone system are investigated. One is the VLSI design of adaptive equalizerand the other is the decoding algorithm of convolutional coding. In the adaptive equalization, a multiple-training LMS bi-directionalalgorithm with fractionally-spaced decision feedback structure(MT-LMS bi- directional FSDFE) is applied. We propose thecustomized- programmable architecture with a hierarchical-FSM controllerto realize it. Simulation shows the proposed equalizer can achieve 2.996%BER at vehical speed of 80 km/hr. We also implement the proposed equalizerin FPGA. The hardware can be operated at 1.5552 MHz within operating timeof 1.38 slot in each frame and occupy 2765.5 logic cells in Altera's FPGA(about 1,4000 gate counts in ASIC). Besides, both the modified bi-directional viterbi algorithm andthe bi-directional tail-biting algorithm are proposed to decode theconvolutional codings in IS-54 system. With the bi-directional traces,decoder can combat the interference of the burst noise appearing in themiddle of the slot. Simulation shows that proposed bi-directional decodingalgorithm has better error-correct ability than unidirectionaldecoding algorithm has that can achieve 1.36% BER at vehical speedof 80 km/hr.