Full metadata record
DC Field | Value | Language |
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dc.contributor.author | 康宗弘 | en_US |
dc.contributor.author | Kang, Tzung-Hung | en_US |
dc.contributor.author | 吳重雨 | en_US |
dc.contributor.author | Chung-Yu Wu | en_US |
dc.date.accessioned | 2014-12-12T02:17:31Z | - |
dc.date.available | 2014-12-12T02:17:31Z | - |
dc.date.issued | 1996 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#NT850428093 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/61965 | - |
dc.description.abstract | 在本論文中,提出一個八位元1.2伏特62.5MHz及一個十位元1.2伏特125 MHz的電流輸出式數位至類比轉換器。此種數位至類比轉換器是利用臨界 電壓補償式電流源來達成十位元所需的高精確度電流輸出。臨界電壓補償 式電流源是根據區域性吻合的概念,將各個電流源之間由於臨界電壓的差 異用鄰近的電晶體加以補償,使產生的誤差降到最小,且不需用到複雜的 電路,因此極適合低電壓電流源使用。另外,此數位至類比轉換器應用了 兩級的架構來減少所需的單位電流源。八位元的數位至類比轉換器只需40 個電流源,而十位元只需64個電流源。經量測此八位元之數位至類比轉換 器轉換速率可達62.5MHz,功率消耗15毫瓦,誤差在0.5個最小有效位元之 內。由於此數位至類比轉換器運用了許多電壓參考源,因此也探討了電壓 參考源的使用。本篇論文中亦設計了一個管線化電流式類比至數位轉換器 。此類比至數位轉換器不使用取樣保持電路,而讓訊號自然傳遞,因此如 何使各位元的資料同步輸出以及解決訊號傳遞時產生的雜訊成為主要的關 鍵。模擬結果顯示此類比至數位轉換器在50KHz的輸入頻率下有八位元的 精確度,轉換速率約為60MHz。 In this thesis, 1.2V 8-bit and 1.2V 10-bits high-speed CMOS D/ A convertersare designed and fabricated by 0.8-um double-poly double-metal(DPDM) CMOStechnology and 0.5-um DPDM CMOS technology, respectively. In these D/Aconverters, the threshold- voltage compensated current source is used in the two-stage current array to reduce the linearity error caused by inevitable current variations of the current sources. In the two-stage weighted currentarray, only 32 master and 8 slave unit current sources are required in the8-bit D/A converter, 32 master and 32 slave unit current sources arerequired in the 10 bits D/A converter. Thus silicon area and stray capacitancecan be reduced significantly. Experimental results of the 8-bits D/A convertershow that a conversion rate of 62.5 MHz is achievable with differential andintegral linearity errors of 0.32 LSB and 0.45 LSB, respectively. The powerconsumption is 15 mW for a single 1.2V power supply. The rise/fall time is7 ns and the full-scale settling time to +1/2 LSB is within 16 ns. The chip area is 2.9 mm x 1.2 mm. The 10-bits D/A converter is under fabrication, too. A pipelined current-mode Analog-to-Digital Converter is also proposed and designed in this thesis. No sample-and-hold circuit is used in the A/Dconverter and the signal is transmitted freely. Therefore it becomes the keypoint to generate digital outputs synchronously and reduce the noise duringthe signal transmission. From simulation results, it is shown that theproposed A/D converter has 8-bit resolution in 50kHz input bandwidth and theconversion rate is 60MHz. | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.subject | 互補式金氧半 | zh_TW |
dc.subject | 數位至類比 | zh_TW |
dc.subject | 類比至數位 | zh_TW |
dc.subject | 轉換器 | zh_TW |
dc.subject | CMOS | en_US |
dc.subject | Digital-to-Analog | en_US |
dc.subject | Analog-to-Digital | en_US |
dc.subject | Converter | en_US |
dc.title | 互補式金氧半高速數位至類比及類比至數位轉換器之設計及分析 | zh_TW |
dc.title | The Design and Analysis of High-Speed CMOS Digital-to-Analog and Analog-to-Digital Converters | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
Appears in Collections: | Thesis |