完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 劉仲 | en_US |
dc.contributor.author | Liu, Chung | en_US |
dc.contributor.author | 葉清發 | en_US |
dc.contributor.author | Ching-Fa Yeh | en_US |
dc.date.accessioned | 2014-12-12T02:17:31Z | - |
dc.date.available | 2014-12-12T02:17:31Z | - |
dc.date.issued | 1996 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#NT850428098 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/61971 | - |
dc.description.abstract | 複晶矽薄膜電晶體用於大面積玻璃基板之平面顯示器是當前極重要的 趨勢。在本論文中,主要分為三個部份。 第一個部份是利用電漿浸入離子佈植 (Plasma Immersion Ion Implantation, PIII)取代傳統的離子佈植,應用在複晶矽薄膜電晶體。 PIII doping 在效率上及均勻度 (uniformity)方面有優越的表現, 且適合應用在大面積基板上,我們對其雜質活化的條件對元件特性的影響 ,有廣泛的探討。 第二部份是改良液相沈積矽氧化膜 (LPD) 所形成的閘極絕緣層,以達成 改善薄膜電 晶體的特性。由於液相沈積矽氧化膜在沈積於複晶矽之前, 必須先有一層薄矽氧化膜在複晶矽表面,因此我們嘗試使用極短時間快速 高溫退火所形成之薄矽氧化膜,取代傳統RCA clean 所形成的薄矽氧化膜 ,如此製作成的薄膜電晶體有較佳的電特性。此外,在沈積閘極絕緣層之 後,我們也嘗試使用極短時間的快速高溫退火來改善液相沈積矽氧化膜的 特性。我們並對於這些不同條件的元件,在信賴性方面有詳細的探討。 第三部份我們嘗試在室溫下成長陽極氧化閘極矽氧化膜,利用此技術所製 作的複晶矽薄膜電晶體,具有不錯的電特性,顯示陽極氧化技術,對於未 來低溫製程複晶矽薄膜電晶體的應用上,有極大的潛力。 Fabricating low-temperature processed poly-Si thin film transistors on large area glass substrate is of great interest for flat-panel liquid crystal displays. In this work, some novel key technologies for improving poly-Si TFT performance have been studied. There are three subjects in this thesis. In the first part, the plasma immersion ion implantation (PIII) technology is utilized for source/drain doping to replace conventional ion implantation. Some advantages of PIII doping include high efficiency and excellent uniformity. PIII is suitable for TFTs on large area substrate because of the large area plasma source. The dopant activation conditions of PIII doping and comparison of PIII with conventional ion implantation have been studied in this part. In the second part, we improve poly-Si TFT performance by improving the quality of liquid phase deposited (LPD) gate insulator. Before the LPD oxide deposited in the poly-Si surface, a thin pre-oxide layer must exist in the poly-Si surface. We use RTP at very short time forming the LPD pre-oxide layer to replace the conventional LPD pre-oxide layer formed in RCA cleaning HCl+ H2O2 solution. The poly-Si TFTs with the novel method exhibit better characteristics than conventional devices. We also change the gate oxide post- anneal conditions by short time RTP to improve LPD gate oxide quality. Moreover, the reliability of these devices with different gate oxide conditions is also studied in detail. In the third part, a novel anodic oxide is formed as the gate insulator of poly-Si TFTs. The formation of anodic oxide is at room temperature. The poly-Si TFTs with anodic oxide as gate insulator exhibit well performance and would have great application potential for low-temperature processed liquid crystal displays. | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.subject | 複晶矽薄膜電晶體 | zh_TW |
dc.subject | poly-Si TFT | en_US |
dc.title | 複晶矽薄膜電晶體關鍵技術之研究 | zh_TW |
dc.title | The Research of Poly-Si TFT Key Technologies | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
顯示於類別: | 畢業論文 |