背閘極偏壓對深微米MOSFET熱電子引致閘極電流注入之影響

Abstract

電晶體中由通道引致的二次電子入射所引發的閘極電流(CISEI),特別 在低電壓下此種CISEI機制是閘極電流的主要成因,同時此機制是與背閘極 偏壓強烈相關的函數. 一個新的解析模型首次被發展出來且能成功地重現 不同大小的元件在不同偏壓下的實驗結果. 此模型亦對CISEI的機制提供 了透徹的瞭解:通道電子和晶體衝擊離子化所產生電洞, 這些電洞下流至 基座同時衝擊離子化產生二次電子, 二次電子回授至閘極下的界面同時從 背閘極偏壓引致的垂直電場及通道封閉區域的水平電場獲致足夠的能量克 服矽和二氧化矽間的能障而形成閘極電流.此模型可進一步地當做應用 CISEI為寫入機制的非揮發性記憶體元件設計的有效工具 This thesis extensively explores the gate current by channel initated secondary electron injection(CISEI) in 0.35um gate length n-type LDD MOSFET's.The CISEI mechanism is observed to dominate the gate current especially at low supply voltage operation, and is found to be a strong function of back gate bias. A new analytic model has been for the first time developed and has successfully reproduced all experimental data from three different device sizes each at different bias conditions. This model also provides a transparent understanding of the CISEI mechanism: the channel electrons impactionize the lattice and create the holes flowing down to the substrate; then secondary electrons are generated via impact ionization by these holes and feed back to the surface beneath gate; simultaneously the secondary electrons gaining the energy from the back-gate bias induced vertical field as well as from the pinch-off lateral field, enough to overcome the Si/SiO2 barrier height and constitute the gate current. This model can further serve as a useful tool for low voltage nonvolatile memory device design.