基座交連特性量測及低於1伏電壓參考源之實現

Abstract

這篇論文探討了兩個主題﹕一個是在共用矽基座之中的交連效應﹐另外一 個則是低於一 伏之參考電壓源的實現。隨著目前IC技術的快速發展﹐將 相同矽基座之中的類比及數位 電路結合在一起的混合式電路是目前實現 一個複雜或高密度結合系統的趨勢。快速交換 的信號﹐像是在數位電路 之中的脈波信號﹐會經由MOS電晶體中的P-N接面﹐通過基座中 的電阻而 擾亂基座的電位﹐進而影響了在相同基座中類比電路的精確信號。另外一 個我 們也觀察到的效應是在較短通道長度之MOS電晶體中的熱載子效應。 我們使用外加的電壓源順偏了在N型MOS電晶體汲極/源極至P型基座(P- substrate)及在P型MOS電晶體中P型擴 散區至N型基座(N-well)的P-N接面 以便模擬熱載子的現象。大量的熱電子或熱電洞因而 由這些順偏的P-N接 面射出並經過基座流向其他的電路。我們使用了0.5um DPDM CMOS製 程的 測試晶片做了一個實驗來探討兩個有關基座交連的問題﹕一個是直接電容 性的交連 問題﹐另一個是熱載子效應。在測試晶片中的取樣/保持電路被 用來當做"類比電路"﹐而單獨一個N型MOS電晶體或是P型MOS電晶體用來當 做"數位電路"。在取樣/保持電路中﹐我們使用不同的操作參數包含脈波 信號的上升/下降時間﹐電路的操作電壓﹐"數位電路"和"類比電路"之間 的距離來觀察因基座交連造成的誤差電壓。我們也觀察並記錄了取樣/保 持電路的輸出波形。我們探討的第二個主題是一個低於1伏參考電壓源的 設計。參考電壓源可以被應用在許多的資料截取系統﹐像是數位類比轉換 器(A/D converter)。許多的研究已經發展出高於1伏的參考電壓產生器。 高於1伏的參考電壓適合用於目前5伏或3伏的 電路設計﹐但對於以後1.5 伏至2.5伏的操作電壓而言顯然是太高。除此之外﹐一個精確 的參考電壓 源還需要對溫度及操作電壓源具有相當的穩定性。我們在這篇論文之中提 出 了一個和溫度及操作電壓無關﹐低於1伏的輸出電壓﹐且操作於低電壓 及低電流的參考電壓電路。這個電路在室溫及1.2伏操作電壓下的輸出電 壓是0.535伏﹐其溫度係數是26.7 ppm/c。另外﹐一個用相同架構完成的 負電壓產生器﹐在室溫及1.3伏操作電壓下的輸出 電壓是-0.6016伏且溫 度係數為23.76 ppm/c。在正電壓產生器中由於操作電壓的變動而 產生的 輸出電壓變化是0.603mV/V﹐而在負電壓產生器之中的則是0.701mV/V。 The thesis explores two topics: one is on the substrate coupling effect in thecommon silicon substrate, and another is the chip implementation of a sub 1-V voltage reference. With the fast development of present IC technologies, the mixed-mode circuit that combines digital and analog circuits together on the common silicon substrate is the current trend to implement a complex or high compactness system. Fast switching signal, like the clock signal used in digital circuit can perturb the substrate potential through the capacitance in any P-N junctions of MOS transistors, passing through the resistance of substrate and affecting the accuracy signal of the analog circuits on the samedie. Another effect concerning hot carrier injection in short channel length MOS transistors has also been observed. We simulate the hot carrier phenomenonby using the external voltage to forward bias the P-N junction between the drain/source and P-substrate in N-channel MOS transistors as well as the N-well-to- P+ diffusion in P-channel MOS transistors. Therefore, a large amount of hot electrons or hot holes can inject from these forward biased P-N junctions and flow through substrate to other circuits. An experiment has beendone to explore the substrate coupling problem due to these two factors: the direct capacitive coupling and the hot carrier effect through a test chip fabricated on the 0.5um DPDM CMOS process. The sample/hold circuit on this chip is used as the "analog" circuit and the single N-channel or P-channel MOStransistor serve as the "digital" circuit.Different operation parameters, suchas the rise/fall time and the frequency of the clock signal,the supply voltage,and the distance between "digital" and "analog" circuits are thoroughly considered to better observe the error voltage on the sample/hold circuit due to substrate coupling. The output waveforms are also observed and recorded. The second topic is to design a sub 1-V voltage reference circuit. The voltage reference can be applied in many data acquisition systems, like the A/D converter. Many works have been done to develop the above 1-V reference voltages based on bandgap reference. The above 1-V voltage reference is suitable for present 5V or 3V circuit design, but is too high for future design in 2.5V to 1.5V supply voltages. In addition, the temperature stability is critical in the accuracy of the voltage reference, as well as the stability in supply voltage. In the thesis, we present a new circuit to offer a temperature and supply voltage independent, sub 1-V, and low supply voltage and low current voltage reference. The output voltage is 0.535V for 1.2V supply voltage at room temperature, and the temperature coefficient is 26.7 ppm/c . For the negative voltage reference based on the same architecture, the output is -0.6016V and the temperature coefficient is 23.76 ppm/c. The output variation due to supply voltage variation is 0.603 mV/V and 0.701 mV/V in the positive and negative voltage references, respectively.