省電型電路之設計與應用

Abstract

低功率高品質之超大型積体電路為設計者追求之目標。混合式電路中常使 用的電源供應和介面電路有直流電壓轉換、數位信號位階轉換、和類比信 號輸出等電路，是本論文省電設計探討的對象。本論文共設計了三個晶片 ，都已成功的驗證，其中包含(1)應用在串列資料通信正負雙電荷充電式 電源功率效益改善；(2)應用在數位電路的高速、省電TTL至CMOS輸入驅動 器；(3)應用平面顯示器資料線驅動器之低功率B類驅動放大器。(1) 首先 ，將用於信號位階轉換電路設計成頻率轉換電路，並使正負雙電荷充電式 電源的工作頻率會隨負載自動改變，頻率變動區間為100Hz至25KHz。因而 ，達成電荷充電式電源功率效益改善之目標。當最大負載電流為12mA，其 輸出正電壓大於6.5V和負電壓小於-6V，符合RS-232C串列通信應用之EIA 標準。另外，為使電荷充電式電源開始工作時，能正常工作和避免電晶体 被破壞，起動電路被設計在同一晶片上。不重疊雙相時序和開關電晶体速 度不同之電路設計，可消除和減少短路功率消耗。實驗證明新的電荷充電 式電源實際獲得兩相好處是：(i)電源功率效益改進從2%至32倍之多；( ii)電晶体的崩潰電壓從19.2V降到17V。(2) 本論文設計出一分離式自偏 電壓差動放大器之信號位階轉換電路，在受到半導体製程變動影響和電源 電壓從3.3V改變至5V時，仍具有低功率消耗、高速運行、和邏輯臨界電壓 變化較小之特性。在與其它三種信號位階轉換電路模擬分析，發現信號頻 率高於21MHz時，新的信號位階轉換電路功率消耗為最少。實際驗證中， 當電源電壓是5V和3.3V時，邏輯臨界電壓變化分別為+-24 mV和+-16 mV。 換句話說電源電壓從3.3V改變至5V時，邏輯臨界電壓變化僅為10mV。當電 源電壓是5V和工作頻率是53MHz時，功率消耗則為0.37mW和電路延遲時間 為0.37nS。當電源電壓是3.3V和工作頻率是47MHz時，功率消耗則為0.14 mW和電路延遲時間為0.51nS。(3) 最後，以比較器取代傳統輸出驅動器中 的誤差放大器，設計出一低功率B類輸出驅動器，可應用於平面顯示器中 。由於比較器的輸出為數位信號，當輸入電壓等於輸出電壓時，可將輸出 級的電晶体完全關閉，就不會有靜態工作電流存在，而達到省電的效果。 實驗證明輸出驅動器的靜態工作電流為54uA。當電源電壓為5V和負載電容 為600pF時，輸出信號最大輸入偏差值為 +-mV和擺幅範圍為0.5V至5V。另 外，對輸出信號擺幅範圍為4V之穩定時間是8微秒，符合86赫茲框架掃瞄 率之1204*1280素元液晶顯示器所須規格。 Low power design with high performance is major strend for CMOS VLSI system design. In mixed mode circuits, the voltage generations, level conversions, and output analog signals are essential. This thesis describes the design of power saving voltage generator, level converter, and buffer amplifier which are components of mixed mode circuits. The designed components include: (1) a power efficient charge pump which is used to generate dual high voltage for RS-232C applications; (2) a power efficient, high speed TTL-to-CMOS input buffer which is used in level conversion stage for CMOS digital circuits applications; (3) a low power CLASS-B output buffer which is used as data line driver for LCD or FED applications. Conventional charge pump circuits use a fixed switching frequency which leads to power efficiency degradation for loading less than the rated loading. This thesis proposes a level shifter design that also functions as a frequency converter to automatically vary the switching frequency of a dual charge pump circuit according to the loading. The switching frequency is designed to be 25K Hz with 12 mA loading on both inverting and non-inverting outputs. The output voltages of the dual charge pump circuits The output voltages of the dual charge pump circuits are V+ > 6.5 V and V- < -6 V which meet the specification of EIA standard for serial communication (RS-232C applications). The switching frequency is automatically reduced when loading is lighter to improve the power efficiency. The frequency tuning range of this circuit is designed to be from 100 Hz to 25 KHz. In addition, a start-up circuit is included to ensure proper pumping action and avoid latch-up during power-up. A non-overlapped two phase clocks and buffer is used to eliminate short-circuit power dissipation. The measured results show that the new charge pump has two advantages: (1) the power dissipation of the charge pump is improved by a factor of 32 at no load and by 2% at rated loading of 500ohm; (2) the breakdown voltage requirement is reduced from 19.2V to 17V. Secondly, a separately self-biased differential amplifier (SSDA) TTL-to-CMOS input buffer is proposed which has low power dissipation, high operating speed, and its logic threshold voltage is less sensitive to process and supply voltage variations. Its logic threshold voltage does not change when supply voltage is changed from 3.3V to 5V, making it suitable for 3.3V/5V dual voltage applications. Its simulated performances are compared with those of inverter, SPSIB, and CSDA buffers. The SSDA buffer has the lowest power dissipation for inputs higher than 21MHz. Its operating speed is comparable to the invert, and much faster than the CSDA and SPSIB buffers. The measured logic threshold voltage variations due to process are +-24mV for 5V supply, and +-16mV for 3.3V supply. Its logic threshold voltage variations due to supply voltage variation from 3.3V to 5V are within 10mV. With 5V supply, 53MHz input, and driving another SSDA buffer, its power dissipation is 0.37mW and delay is 0.45ns. With 3.3 V supply and 47MHz input, its power dissipation is 0.14mW and delay is 0.51ns. A low power Class-B output buffer using comparator for driving large capacitance in flat panel display is presented in this thesis. Due to the large number of output bufferA low power Class-B output buffer using comparator for driving large s on a column driver chip, the quiescent current of the output buffer must be reduced. A comparator which produces full-swing digital output is used, in stead of an error amplifier using conventional output buffer, in the negative feedback path to eliminate quiescent current in the last output stage. The measured static current is 54uA. With 5V supply voltage and 600pF load capacitance, the maximum tracking error voltage is +-8mV, the output voltage swing is from 0.5V to 5V. The settling time for 4V swing to 0.2% is 8us, which is more than adequate for driving 1204*1280 pixels LCD panel with 86Hz frame rate.