微處理機之時脈與電源分佈

Abstract

由於資訊化時代的來臨，加上快速進步的積體電路製造技術，人類生 活已脫離不了微處理機的輔助。微處理機在所有的積體電路中，是最複雜 的電路系統，所遭遇的問題也是最多。在本篇論文中，我們探討了高效能 微處理機的兩個設計關鍵─時脈與電源分佈。在時脈分佈設計上，主要面 對的問題為轉換時間 (transition time) 、時脈偏差 (clock skew) 及 相位延遲 (phase delay) 。由於這些問題的存在，降低了系統的工作時 脈速度，進而影響到系統的工作效能。在電源分佈設計上，主要面對的問 題為電壓下降 (voltage drop) 及電壓波動 (voltage fluctuation) 。 由於這兩個問題的存在，使得電源訊號不能維持穩定的電壓，進而使系統 產生誤動作，造成不可預期的後果。而積體電路製造技術的進步，內連線 (interconnection) 的電阻、電容及電感效應問題，更增加了上述問題的 嚴重性。我們參考了學術上及現有高效能微處理機的設計方法，利用簡單 而又有效的方法，來減輕時脈與電源分佈設計時所遭遇的問題，並建立一 套設計與分析流程，使我們能在實際佈局前做好準確的設計與分析，避免 冗長的修正工作。最後，我們利用所建立的設計與分析流程，完成一個實 例的設計與分析。模擬結果顯示，時脈偏差僅為時脈周期(5ns)的1.43%， 電壓下降則為工作電壓(2.5V)的8.63%。 Because of the rapid advance in VLSI technology in recent years, contem-porary high-performance microprocessors contain millions of transistors and operate at a clock rate of hundreds of MHz. In this thesis, we investigate two important design issues of microprocessor design: clock and power/ground distribution. The major points in clock distribution design are to minimize clock transition time, clock phase delay, and clock skew. The major points in the power/ground distribution design are to minimize voltage drop and voltage fluctuation on the chip. In this thesis, an effective pre-layout design flow is developed to design the clock distribution network and the power/ground distribution grid for high-performance microprocessor design. The design flow uses simple algorithms and a reasonable circuit model to obtain reasonable results before physical layout design, and thus reduce the tedious fixing work in layout design. In addition, the design flow is applied to an example micro-processor that consists of 8 millions of transistors. The results show that the clock skew is reduced to 1.43% of the clock cycle (5 ns) and the voltage drop is reduced to 8.63% of the working voltage (2.5 V).