SA-110微處理器設計功能驗證

Abstract

StrongARM SA-110 是一個三十二位元的純量微處理器。在該晶片上它 有著16KB的指令高速緩衝記憶體、16KB的回寫式資料高速緩衝記憶體、一 個寫出緩衝器及二個記憶體管理單元。它是一個分為五個階段的管線式架 構，以求能在單位時間內有高的工作量。SA-110除了顯示了高效能外，由 於它的面積小及功能簡單使得它亦同時具備了省電的特色，特別適用於那 些對可攜性要求高、耗電量低的系統。SA-110的記憶體處理單元支援了傳 統Two-Level Page Table結構且做了一些擴充。就一個小且價格導向的晶 片來講，這些特色使我們對它的高指令執行率及即時反應印象深刻。 在 這篇論文中，我們要對我們根據 StrongARM 規格書所設計的微處理器做 功能驗證。在由上而下的設計方式下，採儘量不對原 Verilog 程式碼做 更動的方式來驗證其正確性。本愈早驗證、愈容易發現且更正錯誤的原則 ，完成之前就可以先期做驗證卻不需煩惱冗雜的驗證工作。 The SA-110 is a general-purpose, 32-bit RISC microprocessor with a 16 KB instruction cache(Icache);a 16 KB write-back data cache(Dcache);a write buffer; and two memory management unit( MMU) combined in a single chip. The five-stage pipelined distributes tasks evenly over time to remove bottlenecks, ensuring high throughput for the core logic. The SA-110 onchip MMU supports a conventional two-level page-table structure, with a number of extensions. For a small and cost-effective chip, these features result in a high instruction throughput and impressive real-time response. In this thesis, we will verify the microprocessor which is designed according to the StrongARM specification. Under Top-Downsave module least. According to the policy of "finding the design bugs as soon as possible will be easier to fix bugs ", we creating a unit-level simulation environment, the authors are able to do large amounts of testing(sometimes exhaustive) before the whole chip has been designed.