複晶矽薄膜電晶體關鍵製程技術之研究

Abstract

利用複晶矽薄膜電晶體製作畫素元件及週邊驅動電路已成為發 展液晶顯示器的重要技術。在本論文中，將探討製作複晶矽薄膜電晶體的 幾個關鍵製程技術，包括：閘極絕緣層、缺陷的填補及源極/汲極的佈植 。 首先，我們使用離子披覆 (Ion Plating) 的方法在室溫下沈 積優良的二氧化矽膜作為閘極絕緣層。藉由橢圓測厚儀、霍氏轉換紅外光 譜儀及蝕刻率的量測，可發現在室溫下沈積的離子披覆二氧化矽膜是一種 高密度、帶有strained bond的薄膜。經由電容-電壓及電流-電壓等電容 電特性的分析，可知離子披覆二氧化矽膜具有低漏電流、高崩潰電場及低 界面陷阱密度等優異特性。此外，離子披覆二氧化矽膜在氮氣中經過高溫 退火處理後，其特性會趨近於熱氧化膜的特性。此新式的離子披覆二氧化 矽膜已成功地應用於低溫製作複晶矽薄膜電晶體的閘極絕緣層，而且獲得 優異的元件特性。 在缺陷填補方面，我們在以離子披覆二氧化矽 膜作為複晶矽薄膜電晶體的覆蓋層的同時，利用鍍膜腔體內既有的氧氣電 漿對複晶矽主動層內的缺陷作填補。以離子披覆二氧化矽膜作為覆蓋層之 複晶矽薄膜電晶體的特性優於以電漿輔助式化學氣相沈積二氧化矽膜作為 覆蓋層之複晶矽薄膜電晶體，由此可證實在沈積離子披覆二氧化矽覆蓋層 的同時，確實有氧氣電漿作為缺陷填補之用。此外，我們也對以離子披覆 二氧化矽膜作為覆蓋層的複晶矽薄膜電晶體作氨氣電漿處理以進一步填補 缺陷。由於許多tail state及deep state已被氧氣電漿所填補，所以氨氣 電漿處理只能填補剩下的少許deepstate，因此元件特性的改善不明顯。 在本研究中，我們發現離子披覆氧氣電漿處理比氨氣電漿處理具有更優異 的填補效率。而且，以離子披覆氧氣電漿處理過之複晶矽薄膜電晶體也具 有較優異的信賴性，即使在100℃下以20伏特測試1E4秒，元件特性也不會 變差。 除了以離子披覆氧氣電漿作為缺陷填補的方法外，在本論 文中還利用感應耦合式電漿 (Inductively Coupled Plasma, ICP) 作為 氫化處理之用。感應耦合式電漿具有很高的電漿密度，可大幅縮短氫化時 間。此外，我們也在氫氣電漿中加入氬氣，以促進氫氣的離子化。在本研 究中，我們會對氬氣促進氫化的機制及氫/氬混合電漿的特性做深入的分 析。此外，我們也對氫化過的複晶矽薄膜電晶體進行退火處理，此退火處 理可進一步加強填補效率、消除閘極絕緣層內的氫離子及改善元件的信賴 性。 最後，本論文提出一種新式的源極/汲極佈植技術，即電漿 沈浸式離子佈植(Plasma Immersion Ion Implantation,PIII) 技術。電 漿沈浸式離子佈植可提供源極/汲極足夠的摻雜濃度及接面深度。此外， 由於在摻雜佈植的過程中也有氫離子的佈植，可促進摻雜的活化，比傳統 離子佈植具有較低的活化溫度及較短的活化時間。電漿沈浸式離子佈植過 的區域具有低的片電阻，而且無寄生電阻的問題，可提供優良的源極/汲 極。以電漿沈浸式離子佈植製作之複晶矽薄膜電晶體的特性可媲美傳統離 子佈植製作之複晶矽薄膜電晶體。 The use of polycrystalline silicon thin-film transistors (poly-Si TFTs)as pixel switching elements and peripheral driver circuits is an important issue in the development of active- matrix liquid-crystal displays (AMLCDs). In this thesis, several key technologies for the fabrication of poly-Si TFTs are described, including gate insulators, defect passivation, and source/drain doping. To develop excellent silicon oxide films as gate insulators usinglow temperature method, ion plating (IP) oxide is investigated. Physicochemical characterizations of the IP oxide are studied using ellipsometry, Fourier transform infrared spectrometry and P-etch rate measurement. The IP oxide is a high-density dielectric with strained bonds. Electrical characterizations are also analyzed using capacitance-voltage and current-voltage techniques throughmetal-oxide-semiconductor (MOS) capacitors. The IP oxide has a low leakage current, a high breakdown field and low interface state density. In addition, IPoxide annealed in N2 ambient is also studied. After high- temperature annealing,the characteristics of IP oxide become comparable to those of thermal oxide.The novel oxide film is successfully applied as a gate insulator to low-temperature processed poly-Si TFTs which exhibit excellent characteristics. For defect passivation, a novel method has been developed using IP oxidesas capping layers of poly-Si TFTs. The characteristics of these novel TFTs aresuperior to those of TFTs with PECVD TEOS capping oxides due to an in-situ O2-plasma passivation effect during IP oxide deposition. The passivation effect of a NH3 plasma on the novel devices is also studied. Since many tail states and deep states have been passivated by O2-plasma, and only some deep states canbe further passivated after NH3-plasma treatment, the improvement in the novel TFTs by NH3 plasma is not evident. The in-situ IP O2 plasma shows a betterpassivation efficiency on trap states than the NH3 plasma. Poly-Si TFTs with IP capping oxides are hardly degraded even when stressed with a bias of 20 V at 100Cfor 1E4 s. In addition to the in-situ O2-plasma passivation, anothermethod for defect passivation is developed using an inductively coupled plasma(ICP) source. Experimental results indicate that ICP has a higher plasma densit,thereby capable of significantly shortening the hydrogenation time. Moreover,to impel the ionization of hydrogen, Ar gas is also introduced to H2 plasmaduring hydrogenation. The mechanism of Ar enhanced hydrogenation and the characteristics of H2/Ar mixed plasma are investigated. In addition, the post-hydrogenation anneal is utilized to further enhance passivation efficiency,eliminate the mobile hydrogen ions within gate oxide, and improve the reliabilityof TFTs. Finally, plasma immersion ion implantation (PIII) is utilizedfor source/drain doping on poly-Si TFTs. PIII doping can provide enough dopantconcentration and junction depth for source/drain. In addition, H2-diluted phosphorus PIII can promote dopant activation more efficiently during RTA at600C than with conventional ion implantation technology. The PIII doped regionsexhibit low sheet resistance without parasitic resistance, and provide excellentsource/drain regions. The excellent characteristics of PIII doped poly-Si TFTs resemble those of conventional ion implanted ones.