一個適用於超大型積體電路中快速且精確之功率估算方法

Abstract

本論文針對以細胞元(cell)為基礎的超大型積體電路提出新的功率消耗估 測技術。細胞元資料庫包括的細胞元種類很廣，例如有最簡單的基本邏輯 閘(basic gates)，較複雜的複雜性邏輯閘(complex gates)，甚至有更複 雜的巨型模組(macrocells)。本論文中，我們分別對不同型態的細胞元提 出準確的功率消耗模型。對基本邏輯閘和複雜性邏輯閘而言，所提出的功 率消耗模型不僅可以包含輸出端信號轉換所消耗的功率，也可以有效地估 算中間節點因信號轉換所消耗的功率。對巨型模組而言，我們提出兩個功 率消耗模型。第一個模型可以把模組內所有節點因穩態信號轉換所消耗的 功率完全的考慮進來。而為了降低模型的複雜度，我們提出第二個模型， 這個模型雖然忽略模組內少數節點信號轉換所消耗的功率，但是其準確度 依然很高。 根據所提出的功率消耗模型，我們已經建立一個功率特性化 與功率估測的環境。在功率特性化方面，我們建立一個自動化特性分析系 統來為各個細胞元做功率特性化分析。在功率估測方面，我們將功率估測 系統架構在一個商業用的邏輯模擬器Verilog-XL上。由實驗驗證得知，我 們的功率估測系統可以估得近似SPICE的準確度，而且在速度上平均而言 比SPICE快百倍以上。 在本論文的最後一部份，我們將先前所提出的功率 消耗模型應用到一個新的功率最佳化技術。這個技術主要是將邏輯閘中電 晶體的排列順序做有效的重整，以達到降低功率消耗的目的。我們已經提 出兩個新的方法來做電晶體的排列重整。實驗結果告訴我們，這兩個方法 平均而言不僅可以降低9%的功率消耗，同時也可以降低2%的電路延遲。 In this dissertation, we have presented accurate power consumption models for the CMOS cell libraries consisting of basic standard cells and complicated macrocells. In the standard cells, for both basic and complex gates, a modified state transition graph called STGPE is proposed to model the signal transitions of the internal nodes and the output node. For macrocells, two new power modeling techniques are also proposed. The first one is called a complete power modeling technique which selects a subset of the primary inputs and internal nodes in a macrocell as the state variables to build a state transition graph (STG). These state variables can model the steady-state transitions of the internal nodes completely. In order to further simplify the complexity of the STG, an incomplete power modeling technique is proposed. Without losing much accuracy, the property of compatible patterns is exploited for both techniques to further reduce the number of edges in the STG. To develop a cell-based power estimator, power characterization is a must step. We have built an automatic power characterization system for characterizing the energy associated with each edge in the STG's of each library element. Our power estimator is embedded in an event driven logic simulator VERILOG-XL that is used as the simulation platform to calculate the switching activities of the nodes in a circuit. Experimental results show that our power estimation techniques can provide SPICE-like accuracy while the CPU time consumed is more than two orders of magnitude less. Based on the STGPE model, a transistor reordering technique is proposed to reduce the power consumption in the CMOS circuits. To find the best transistor ordering, a state enumeration method and a heuristic method are discussed. For a logic gate, according to the input transition waveforms obtained by logic simulation, the state enumeration method evaluates all possible transistor permutations to find the best ordering with minimal power consumption. In the heuristic approach, we derive some simplified power consumption equations for each internal node in terms of the transition probabilities of the inputs, and then evaluate all possible transistor permutations to obtain the desired ordering. Experimental results show that both approaches can achieve 9% power reduction and 2% improvement in circuit delay on average.