UHF波段低相位雜訊振盪器設計之研究

Abstract

在本論文中，相位雜訊在UHF波段振盪器將會被徹底的研究，特別是隨電 壓改變 電晶體的接面電容會被仔細研究，這部份是Leeson*s model所沒 提及的。相位雜 訊使用非線性電腦模擬軟體中的harmonic balance分析 計算，由接面電容所引起 的雜訊可經由SDD ( Symbolical Defined Device) 的技巧利用電腦來計算，本 文也說明完成低相位雜訊振盪器所 需的條件。利用模擬結果完成一使用實際的元 件作成2.5 GHz的振盪器， 在偏移主頻10 KHz時，為-98 dBc/Hz，在商業用途上 是相當好製作。 In this thesis, the phase noise of oscillator in UHF band is intensivelystudied. The part from voltage-dependent junction capacitance of transistor are carefully studied, which is not discussed in Lesson's model. The pahse noise is calculated by nonlinear CAD program with harmonic balance method. The noise from junction capacitance is calculated by SDD technique. The condition for achieving low phase noise are elucidated. A low phase noise oscillator by lump element at 2.5 GHz is fabricated, base on the simulation. The phase noise at 10KHz offset is about 98 dBc/Hz, which is quite good for commercial application.