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dc.contributor.authorChen, MJen_US
dc.contributor.authorHo, JSen_US
dc.date.accessioned2014-12-08T15:01:53Z-
dc.date.available2014-12-08T15:01:53Z-
dc.date.issued1997-04-01en_US
dc.identifier.issn0278-0070en_US
dc.identifier.urihttp://dx.doi.org/10.1109/43.602471en_US
dc.identifier.urihttp://hdl.handle.net/11536/634-
dc.description.abstractIn this paper we introduce a new subthreshold conduction CAD model for simulation of VLSI subthreshold CMOS analog circuits and systems, This model explicitly formulates the back-gate bias effect and preserves the original advantages of the existing four-parameter model while reducing the fitting parameter number down to three, A transparent relationship between the fitting parameters and the process parameters has been derived, and its correlation with a recently widely used CAD model as well as with a well-known two-parameter model has been established, Our extensive measurement work on n-channel MOSFET's has highlighted the potential of the model in handling the variations in the subthreshold I-V characteristics at different back-gate biases arising from process variations, The mismatch analysis has further been successfully performed with emphasis on the reverse back-gate bias effect. In summary, the proposed model can serve as a promising alternative in the area of VLSI subthreshold CMOS analog circuit simulation.en_US
dc.language.isoen_USen_US
dc.subjectback-gate biasen_US
dc.subjectCAD modelen_US
dc.subjectCMOS analog circuitsen_US
dc.subjectmismatchen_US
dc.subjectsubthresholden_US
dc.subjectprocess variationen_US
dc.titleA three-parameters-only MOSFET subthreshold current CAD model considering back-gate bias and process variationen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/43.602471en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMSen_US
dc.citation.volume16en_US
dc.citation.issue4en_US
dc.citation.spage343en_US
dc.citation.epage352en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
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