完整後設資料紀錄
DC 欄位語言
dc.contributor.author傅旭正en_US
dc.contributor.authorHsu-Cheng Fuen_US
dc.contributor.author唐麗英en_US
dc.contributor.authorTong Lee-Ingen_US
dc.date.accessioned2014-12-12T02:19:57Z-
dc.date.available2014-12-12T02:19:57Z-
dc.date.issued1998en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT870031013en_US
dc.identifier.urihttp://hdl.handle.net/11536/63794-
dc.description.abstract良率(yield)是積體電路業者獲利的一個重要指標,為了能快速、有效地提升良率,於是有良率管理(yield management)的提出。良率管理的領域非常廣泛,凡能夠提升良率的方法,都包含在良率管理之中;而良率管理中,最重要的工具就是能夠提供預測功能的良率模式(yield model)。 傳統良率模式因只考慮到缺陷(defect)數目與良率間的關係,所以求出的良率模式無法具有高準確度,而近年來所發展的修正過之良率模式,又因過於複雜而導致實際應用上受到限制。本研究將同時考慮晶圓(wafer)上的缺陷來源、缺陷數目以及缺陷群聚(defect cluster)對於良率的影響,利用類神經網路可建立預測模型的功能,來有效地解決傳統良率模式的精確度問題。此外,因為類神經網路應用簡易,所以本研究利用類神經網路所構建出之良率模式也沒有修正過的良率模式使用過於複雜的問題。 本研究利用新竹科學園區某IC製造廠的實際晶圓資料來說明如何構建本研究所發展的良率模式,並且證明本研究所構建的良率模式,比現有之其他良率模式在預測方面更為準確且應用簡單。zh_TW
dc.description.abstractFor the integrated circuits (IC) manufacturer, the yield of each wafer is a key index to evaluate the profit. Therefore, yield management has been developed to promote the yield quickly and effectively. One of the most important tool in the yield management is the yield model. The conventional yield models considered only the correlation between the defect counts and the yield, consequently, the models can not predict the yield accurately. The prediction becomes worse when the wafer size increases and the defect clustering phenomenon becomes more apparent. Although the modified yield models have better prediction than that of the conventional yield model, the modified yield model are too complicated for engineers to use in practice. This study considers the effects of defect sources, defect counts and defect clustering on wafer and builds a forecasting yield model by using the neural networks. The proposed yield model not only can promote the prediction power efficiently, but also is very easy to implement. The proposed yield model is illustrated by a real case provided by an IC manufacturer in Taiwan to verify the effectiveness of the proposed yield model. Comparisons are also made among the conventional yield models, modified yield models and the proposed yield model.en_US
dc.language.isozh_TWen_US
dc.subject良率zh_TW
dc.subject積體電路zh_TW
dc.subject良率管理zh_TW
dc.subject良率模式zh_TW
dc.subject缺陷zh_TW
dc.subject缺陷群聚zh_TW
dc.subject晶圓zh_TW
dc.subject缺陷來源zh_TW
dc.subjectintegrated circuiten_US
dc.subjectwaferen_US
dc.subjectyielden_US
dc.subjectyield managementen_US
dc.subjectyield modelen_US
dc.subjectdefecten_US
dc.subjectdefect clusteringen_US
dc.subjectdefect source, neural networksen_US
dc.title考慮缺陷來源與群聚現象之積體電路良率模式zh_TW
dc.titleIntegrated Circuit Yield Model with Defect Source and Defect Clusteringen_US
dc.typeThesisen_US
dc.contributor.department工業工程與管理學系zh_TW
顯示於類別:畢業論文