模組化晶圓製造廠物料搬運系統之設計

Abstract

近年來，我國半導體產業所創下的耀眼成績，使得半導體產業儼然成為我國的經濟命脈。然而在同業間競爭逐漸白熱化的情況下，唯有擴充本身的產出以及提高達交能力，才可在半導體製造業中佔有一席之地，而這正是現階段全球半導體業者極力追求的目標。 吳氏等學者[33,34]提出一套模組化同心圓式晶圓廠的理念，本文即是構建在此一理念上，針對其廠區佈置、物流路徑、物料搬運系統及投料派工法則等項目進行設計，接著針對所設計之方案開發其模擬系統並進行績效評估。 在廠區佈置方面，本文採最具效率的流線型(flow line)佈置，並配合物流路徑的設計縮短其搬運距離，以降低生產週期時間。而在物料搬運系統的設計上，本文以避免物流形成系統之限制為主要設計理念，控制搬運車之繞行速率，使其配合瓶頸機台的產出速率；並依瓶頸機台前後之搬運需求做適度的調配，以確保瓶頸機台處之物流順暢。最後，因應批次機台的加工特性，採用六連批的投料原則；而投料速率則以瓶頸機台的產出率為主，配合在製品總量的固定，控制系統中之在製品數量。而模擬結果顯示本文之設計確能達成高產出、低生產週期及低在製品量的目標，對晶圓製造廠之月產量及達交能力的提升上助益匪淺。

In recent years, semiconductor industry becomes the booming industry in Taiwan. The competition between the wafer fabrication factories hence becomes more and more keen. In such environments, enhancing the throughput and delivery performance is the only way to keep the competitive superiority. Wu [32, 33] proposes the architecture for modularized, economical, flexible and automated semi-conductor factory. In this thesis, corresponding design for the plant layout, the path of material flow, the material handling system is proposed , the releasing rule for Wu's modularized wafer fab. A simulation model is built to collect its system performance. For the plant layout, this thesis contrives the facility layout to be flow line in order to reduce production cycle time, and to design the path of material flow so as to shorten material handling distance. For the material handling system, the major idea is to prevent material flow from being system bottleneck. Thus, the cycle time of the monorail traveling is set so as to fit the throughput rate of bottleneck workstation. Also, the priority for moving requests are set according to the status of bottleneck to keep material flow smooth before and after bottleneck. Finally, for the design of releasing rule, the policy of releasing six lots simultaneous is adopted to fit the feature of the batch machine. The releasing rate is set with considerations of the bottleneck's throughput rate, and then adjusted by using fixed-WIP method so as to control the WIP level and the cycle time in an acceptable range. The simulation results show that with such a design, the modularized wafer fab can reach the goal of high throughput, low production cycle time and low WIP level. Such a design makes a contribution in increasing throughput and enhancing delivery ability of the wafer fabrication factories.