完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 蘇育清 | en_US |
dc.contributor.author | Yuh-Ching Su | en_US |
dc.contributor.author | 葉清發 | en_US |
dc.contributor.author | Ching-Fa Yeh | en_US |
dc.date.accessioned | 2014-12-12T02:20:45Z | - |
dc.date.available | 2014-12-12T02:20:45Z | - |
dc.date.issued | 1998 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#NT870428034 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/64317 | - |
dc.description.abstract | 為了降低RC delay, 銅和低介電絕緣材料之製程整合是未來後段製程的重大議題。由於銅在乾蝕刻時生成物不易揮發,傳統的鋁製程已被嵌刻 (Damascene) 製程取代。然而低介電材料蝕刻完之後,在去光阻時會遭受氧電漿損害,因而造成介電值上升以及金屬導線氧化。 在本論文中,我們提出以溫差液相沈積二氧化矽含氟膜當低介電材料MSQ的壁覆蓋層以取代硬光罩製程來解決氧電漿損害問題。此含氟膜具有選擇性成長的特性,它不會沈積在光阻上,因此在去光阻前我們沈積此含氟膜在MSQ側壁上,然後去除光阻。此方法比硬光罩法製程簡單且與雙重嵌刻法相容。由於此膜是在室溫成長所以有極低應力值,並且它有良好的絕緣特性,可降低金屬間的漏電。這種製程技術同時改進了硬光罩以及二氧化矽襯墊層的問題。 此含氟膜在25℃成長時具有最低的介電質(~3.4),最低的硬力值(~41Mpa) 。因此適合用在後段製程。而且只要大約12.7nm的厚度就可抵抗氧電漿損害了。此外,為了提高此膜的抗濕性,我們使用笑氣電漿來作退火處理。 在嵌刻製程中,介電材料的蝕刻是很重要的,我們研究發現MSQ的蝕刻條件可只藉著只調CF4流量和射頻功率來獲得最佳的蝕刻條件。最後,為了去掉MSQ側壁聚合物,我們發展一種兩階段的處理方式,且此法並且不會對MSQ造成損害。總而言之,我們已發展出一種新的無氧電漿損害的嵌刻製程。 | zh_TW |
dc.description.abstract | To reduce RC delay, integration of Cu and low K dielectric is an important issue in future back end of line (BEOL) process. Owing to the etching by-products of Cu are hard to volatile, conventional Al metallization was replaced by Damascene process. However, after low K dielectric patterning, the dielectric will suffer O2 plasma damage during stripping, and result in K value increment and metal line corrosion. In thesis, to replace hard mask process, we propose a method of using TD-LPD FSG a MSQ's sidewall capping layer to avoid O2 plasma damage. This FSG has selective deposition characteristics i.e., it won't deposit on photoresist. Therefore, prior to photoresist stripping, we deposit this FSG on MSQ's sidewalls, then remove the photoresist. This method is more simple than hard mask process and compatible with dual Damascene process. This FSG exhibits low stress property owing to room deposition temperature. Besides, it has good isolating ability, which reduces leakage current between metal lines. The proposed method improves hard mask process and oxide linar process at one time. the film deposited at 25℃ with lowest K value (~3.4), lowest stress value ( ~41Mpa). Therefore, it is suitable to be used in BEOL process. Furthermore, The FSG with thickness ~12.7nm is adequate to withstand O2 plasma damage. Besides, we use N2O plasma annealing to enhance the moisture absorption resistance of the FSG. The dielectric etching process is very important in Damascene process. We found that The optimal MSQ etching recipe can be obtained by adjust CF4 flow rate and RF power value only. Finally, to remove MSQ sidewall polymer, we developed a technique with two-step treatment, and which won't damage MSQ. To sum up, we have developed a novel O2 plasma damage free Damascene process. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 銅 | zh_TW |
dc.subject | 溫差液相沈積 | zh_TW |
dc.subject | 含氟矽氧化膜 | zh_TW |
dc.subject | 低介電常數 | zh_TW |
dc.subject | 氧電漿損害 | zh_TW |
dc.subject | 側壁覆蓋 | zh_TW |
dc.subject | Cu | en_US |
dc.subject | temperature-difference liquid phase deposition | en_US |
dc.subject | SiOF | en_US |
dc.subject | low K | en_US |
dc.subject | O2 plasma damage | en_US |
dc.subject | MSQ | en_US |
dc.subject | sidewall capping | en_US |
dc.title | 極大型積體電路銅製程關鍵技術之研究-銅/溫差液相沈積含氟矽氧化膜/低介電常數MSQ之製程整合 | zh_TW |
dc.title | Investigation of ULSI Damascene Key Process-Process Integration of Cu/Temperature Difference Liquid Phase Deposition SiOF/Low K MSQ | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
顯示於類別: | 畢業論文 |