直接降頻架構在2.4ghz無線區域網路之設計

Abstract

最近的單晶片設計中，直接降頻架構使得矽晶片的大量投入整合成為熱門. 在許多的文章中都有討論到設計時所遇到的直流準位偏差，偶皆的失真和高雜訊的問題。 我們在此篇論文中將討論直接降頻的架構。本文中將用 CMOS 0.35um及 BiCMOS 0.5um 所作的降頻器來討論直接降頻系統的缺點並推導此降頻器。所得到的模擬結果如下，線性度 11.3dBm，轉移增益11.3dB，雜訊增益14.2dB及本地振盪遺漏-88dBm。一有效及快速的補償直流準位偏差的類比電路將被用來減少數位時處理的錯誤率。所提出的架構會符合電子電機協會802.11的歸範。

For the trend of system on chip, direct conversion front end, which possesses highly integration properties, attracts prosperous researches especially with silicon solution. The major design challenges are the DC offset and even-order distortion and flick noise as discussed mainly in most literatures In this thesis, the architecture of direct conversion receiver for 2.4Ghz WLAN is proposed. To convey the major drawbacks of the direct conversion such as DC offset and linearity demand, four types of mixers have been derived and been designed under CMOS 0.35um and BiCMOS 0.5um process. Major specifications simulated includes, IIP3 2.1dBm, conversion gain 11.3dB, NF 14.2dB and LO leakage -88dBm. Efficient technologies to compensate DC offset have also been proposed with simple analog circuitry which provide high speed processing and thus decrease the error rate for further DSP processes. With system link budget analysis, the circuits proposed meet the specifications of 802.11 specifications.