媒體處理器架構之研究

Abstract

隨著多媒體技術的快速發展，多媒體應用已深深影響我們的日常生活。而媒體處理器可以提供這些多媒體應用一個很好的解決之道。 本論文提出一個包含以類ARM為主處理器和一個SIMD向量協同處理器的媒體處理器架構。類ARM主處理器主要扮演著一個系統控制器，它的指令集和ARM7相容。SIMD向量協同處理器由一個乘法單元、一個算術單元、二個載入單元和二個純量單元所組成。結合一個類直接記憶體存取控制器、可分割的乘法及算術單元、分離的載入單元、純量單元和一個共時控制單元，我們的媒體處理器可以減輕主處理器的負擔、產生高度的資料平行度及可達到亂序執行和依序結束的功能。在協同處理器中也支援了多緒頭架構，用來達到高的緒頭平行度。 除了記憶體和暫存器外，全部的模組都是用可合成的暫存器轉換層次硬體描述語言所描述，模擬結果也在本論文中提出。

With the rapidly evolving in multimedia technology, multimedia applications have taken a great influence on our daily life. A media processor is a good solution to these multimedia applications. In this thesis, a media processor is presented for multimedia data processing. It contains an ARM-like mainprocessor and a SIMD Vector Coprocessor (AM-SVC). The ARM-like mainprocessor, which acts as a system controller, is instruction compatible with ARM7. The SIMD Vector Coprocessor consists of one multiplier unit, one arithmetic unit, two load/store units, and two scalar units. Combining with a DMA-like controller, splittable design of multiplier and arithmetic units, separated load/store units, scalar units and a concurrent control unit, our media processor is able to alleviate mainprocessor's burden, exploit high data parallelism, and achieve out-of-order execution and in-order completion. Multithread architecture is also adopted in the coprocessor for exploiting thread level parallelism. All the modules except memory and register files in the design are coded in synthesizable RTL Verilog HDL. Simulation results of AM-SVC are also given in this thesis.