以不同的製程處理所製作之鈦酸鍶鋇薄膜之特性

Abstract

高介電係數的鈦酸鍶鋇薄膜近來成為相當熱門的材料之一. 不論是用在隨機存 取記憶體的電容胞以得到相當高的單位面積電容來增加容積; 或是一方面在取 代傳統二氧化矽超薄氧化層, 利用較厚的高介電係數材料來得到與超薄氧化層 相同的閘極電容特性而不會有過高的穿隧漏電流. 由於以自旋塗佈法所沉積的 鈦酸鍶鋇需在高溫下(600以上)才有結晶態產生而具有高介電係數的特性, 且 其能隙相當低(3~4 eV)使電子容易借由薄膜中的缺陷或是經由與界面電極間的 低能障通過而造成較大的漏電流. 因此本文主要的目的是利用不同的後製程處 理方式來降低薄鈦酸鍶鋇薄膜的漏電流,希望能借由最佳化的製程條件,在不犧 牲介電常數的情況下能有最低的漏電流,期望能達到Gbit級DRAM量產階段的要 求. 文中採用的電漿後處理與快速熱退火製程, 均為與傳統積體電路製程相容 的技術. 因此在不增加成本與複雜度的狀況下是相當適當的選擇. 實驗的另一主題為以BST薄膜作為閘極氧化層的應用. 實驗發現利用快速熱退 火與BST和基板矽晶片間加入阻障層後所製作之閘極堆疊氧化層電容, 其等效 氧化層厚度可達到與高溫氧化層相同厚度的電容, 且具有相近的漏電流值. 唯 其介面雜質濃度與氧化層補捉電荷值仍相當高. 如何有效降介面雜質密度與減 少等效氧化層厚度, 成長高品質的絕緣阻障層將是未來重要的研究目標.

Great efforts have been made for the integration of high dielectric constant BaSrTiO3 (BST) capacitors into DRAM. Conventional oxide/nitride/oxide (ONO) or thermal oxide dielectric will require a film area ratio of approximately 40:1 to maintain the required 35fF storage capacitance/cell. If cell area need be decrease more, the dielectric layer of cell capacitor should be become thinner and will suffer high tunneling leakage current. An alternative approach is to use new material with higher permittivity than conventional dielectric materials . BST is of high interest for this application because of its unique combination of high dielectric constant, low dispersion up to high frequency, and stable operation at high temperature. It is believed that higher annealing temperature will make it crystalization and high dielectric constant, but leakage current also increases spontaneously with increasing annealing temperature because of many factors, for example, bandgap lowing and lower grain boundary resistance. In order to reduce the leakage current of BST without sacrificing its dielectric constant, different kinds of post-treatments are investigated in this study. Plasma-treatment and rapid thermal process (RTP) have been used because they are compatible in CMOS process. Another topic is the gate dielectric application with thin BST films. We find that using RTP annealing with BST/oxide/Si stack structure of capacitor, both EOT(Effect of OxideThickness) of BST stack capacitor and leakage current have been effectively decreased. But the flat band voltage shift which is induced by the drift ions or traping charges in BST films and density of interface states (Dit) are still larger than conventional thermal oxide. Growth of high quality barrier layer in the metal/high-k dielectric/Si structure to suppress inter-diffusion of high-k material and Si will be an important research topic in future for gate dielectric application.