深次微米MOSFET通道引致二次電子閘極電流之研究

Abstract

通道引致二次電子入射機制近來發展出在超大型積體電路中嶄新的應用，特別是在快閃式記憶體中縮小化、低功率、及大量儲存上的應用。這種CISEI機制經證實它在大型記憶體陣列中有低電壓、低電流寫入、緊縮的臨界電壓控制、對過度擦拭的免疫力，以及對重複循環的高忍受度等優點。對現今低功率、高表現的快閃式記憶體而言是種極具吸引力的有利工具。 本論文廣泛地探索了在0.35微米閘極長度之n型態金氧半電晶體中由通道引致二次電子入射的閘極電流。此種CISEI機制是閘極電流的主要成因，特別是在低供應電壓下，同時此機制經發現是背閘偏壓強烈的相關函數。一種內含有兩個主要參數的物理可解析模型被提出來，且此兩參數首次由一個校正過的傳統漂移及擴散解中被萃出。此方法亦對CISEI的機制提供了透徹的了解：通道電子和晶體衝擊離子化所產生電洞，這些電洞下流至基座同時衝擊離子化產生二次電子，二次電子回授至閘極下的界面同時從背閘偏壓引致的垂直電場中獲得主要能量去克服矽和二氧化矽間的能障而形成閘極電流。此模型更可進一步地預測出此二次電子在不同的溫度之下的量及其對下一世代金氧半電晶體的衝擊。

The channel initiated secondary electron injection (CISEI) mechanism has recently found new applications in VLSI area, especially the scaled, low power, mass storage flash memory. The CISEI mechanism has been demonstrated in terms of the benefits like low voltage, low current programming, tight VT control, over-erase immunity in large memory arrays, and high cycling endurance. It is now an attractive candidate for low power, high performance flash technology. This thesis extensively explores the gate current by channel initiated secondary electron injection (CISEI) in 0.35um gate length n-type LDD MOSFET's. The CISEI mechanism is observed to dominate the gate current especially at low supply voltage operation, and is found to be a strong function of back gate bias. A physically-based analytic model is proposed with two key input parameters for the first time extracted from a calibrated, conventional drift-diffusion solution. The way provides a transparent understanding of the CISEI mechanism: the channel electrons impact ionize the lattice and create the holes flowing down to the substrate; then secondary electrons are generated via impact ionization by these holes and feed back to the surface beneath gate; and simultaneously the secondary electrons gaining the energy mainly from the back-gate bias induced vertical field, enough to overcome the Si/SiO2 barrier height and constitute the gate current. This model can be further used to predict the amount of secondary electron gate current under different temperature conditions as well as the impact drawn on the next generation flash technologies.