可用於快閃式記憶體反覆寫入抹除前後之直流與暫態模式

Abstract

藉著電路階級的模擬來完成設計最佳化，在元件的研發中是很重要的一個步驟。電路模擬器作為電腦輔助設計(CAD)的工具，已經廣泛地應用在設計工作中的各個階段。在快閃式記憶元件的設計中，暫態特性是絕對需要的。為了建立起暫態分析的基礎與透徹地了解快閃式記憶元件的操作模式，一個解析的(analytical)閘極電流模式是不可或缺的。此外，為了要模擬快閃式記憶體的電路操作，也必須依賴精準的汲極電流模式。 另一方面 ，反覆地寫入與抹除所造成的傷害將會導致元件性能均勻地退化，因而限制了元件的耐久度(endurance)。反覆寫入抹除所造成的氧化層缺陷，將會降低元件寫入速度與操作窗口封閉(operation window closure)。 在本篇論文中，吾人發展了一精簡的SPICE模式以模擬快閃式記憶體寫入與抹除的動作，以及耐久度的特性。依照吾人新提出的耦合參數萃取方式，可以發展出快閃式記憶體電流電壓模式。更進一步，吾人憑藉著解析的閘極電流模式模擬了快閃式記憶體的暫態特性。而憑藉著對於氧化層缺陷對元件效能影響的了解，吾人可模擬反覆寫入抹除前後的寫入與抹除的暫態特性。最後，將可模擬出反覆寫入抹除後耐久度的特性。

Circuit level simulation for design optimization is a very important step in device development. Circuit simulator as a CAD tool has been extensively used at various design stage. In the flash memory cell, it is crucial for the cell design to obtain the transient characteristics. To form the basics of transient analysis and to fully understand flash memory device operation, an analytical gate current model is needed. In addition, for simulating circuit operation of flash memory cells, an accurate drain current model is also required. Moreover, the program/erase cycling stress is known to cause a fairly uniform wear-out of cell performance, which eventually limits flash memory endurance. Oxide damage generated after cycling will result in cell programming speed retardation and the operation window closure. In this paper, we developed a compact SPICE model for flash memory cells to simulate the programming and erase behavior, and the endurance characteristics. Using the coupling coefficients extracted by our new characterization method, the I-V model of flash memory can be developed. Furthermore, an analytical gate current model which can be used to simulate the transient simulation of flash memory cells was developed. In addition, based on the knowledge of oxide damage effects on device performance, the program and erase transient characteristics before and after P/E cycles can be simulated. Also, the P/E stress induced cycling endurance characteristics can be obtained.