應用分解濾波演算法的新等化技術及相關同步方法

Abstract

本論文提出一類使用分解演算法的盲目等化器以及一個結合此盲目等化 器、載波回復器以及時序回復器的接收器架構。在等化器的部份，降低 複雜度與訓練係數是兩個重要的主題。分解演算法(decomposition algorithm)能簡化等化器在計算迴旋積分部份的複雜度約一半。首先， 我們證明了使用分解演算法架構的最小均方演算法(LMS)在適當的步階常 數(stepsize)的設定下，可以保證其平均值收斂。我們也比較了它與使 用線性濾波器(linear filter)的最小均方演算法間的差異。 接著，我們將分解演算法應用到使用Godard成本函數(cost function) 的盲目等化器。一些簡化的相關的演算法也被提供，包括能消除係數調 整所需乘法的符號(sign)演算法、增進硬體效率的延遲(delayed)演算 法、降低分解演算法乘法複雜度的輸入輸出等比例縮放 (input/output scalling)演算法以及移去不為零平均值的直流消除 (dc removed)演算法等等。 我們研究了這類盲目分解演算法的收斂性質，證明了在無限長的等化器 與一些關於傳輸信號及通道特性的設定下，它的表現曲線(performance surface)只有二組區域最小值。其中一組等化後的通道響應(channel response)全為零，這是不希望的特性；另一組則具有完全等化的效果， 可經由適當的初值設定來達成。而對於相關的簡化演算法而言，我們無 法得到符合的成本函數，事實上也不存在。經由檢查它們的調整係數等 式，我們也獲得了一些對於簡化演算法收斂性質的了解。 我們提出了一個結合載波回復、時序回復以及低複雜度盲目分解等化器 的接收器架構，同時也提供了一個開始的程序，可以將接收器帶進最後 的運作。由於我們設計的等化、載波回復以及時序回復調整方法彼此間 關性相當低，整個接收器的穩定度相當高。 應用於高速數位用戶迴路(HDSL)並使用最小均方演算法的判定回饋等化 器(DFE)的硬體設計已經完成。經由Verilog與Opus VLSI CAD的模擬，我 們證實了這些設計可行。相關的電路配置圖(Layout)設計也已經完成並 製造成積體電路(IC)。經由些微的更變，我們也提出一個可應用到本論 文所提演算法的相關硬體設計。

We present a blind equalizer which based on the decomposition algorithm and a receiver structure with joint the kind of blind equalizer, carrier recovery, and timing recovery. Two important topics in equalizer design are its complexity and its training. The decomposition FIR filtering technique reduces the complexity of the convolution operation in the equalizer to about a half. We find the convergence property of the LMS algorithm based on decomposition algorithm. The algorithm converges in mean behavior by setting suitable stepsize. We also compare the convergence properties between it and the LMS algorithm with linear filter. A family of blind equalizers which utilize the decomposition algorithm is provided. The prototype algorithm in this equalizer family employs the popular Godard cost function. Several simplified algorithms are derived, including sign algorithm which eliminates multiplication in coefficient adaptation, delayed algorithm which increases hardware efficiency, input/output scaling algorithm which reduces the complexity of multiplication, and DC removed algorithm which eliminates DC value of transmitted signal. We also study their convergence properties. For the prototype algorithm, we show that, in the limit of an infinitely long equalizer and under mild conditions on signal constellations and channel characteristics, there are only two sets of local minima on the performance surface. One of the sets is undesirable and is characterized by a null equalized channel response. The other corresponds to perfect equalization which can be reached with proper equalizer initialization. For the simplified algorithms, we are unable to find corresponding cost functions. Indeed, there may not exist corresponding cost functions. Some understanding of their convergence behaviors is obtained via examination of their adaptation equations. We describe a receiver structure with joint timing recovery, carrier recovery and low-complexity blind decomposition equalizer. And we describe a startup sequence to bring the receiver into full operation. The adaptation algorithms for equalization, carrier recovery, and timing recovery are relatively independent, resulting in good operational stability of the overall receiver. The DFE hardware design based on LMS algorithm for HDSL has been accomplished. It is verified with the Verilog and Opus VLSI CAD tools. Layout design of the equalizer chip has been taped out for foundry fabrication. The hardware design of blind decomposition algorithm also is finished by minor modification of the above design.