以FPGA為基礎之三階變頻器研究

Abstract

本論文闡述以空間向量脈寬調變(SVPWM)為基礎之三階變頻器研究。選用SVPWM原理是因與SPWM(正弦波脈寬調變)相比有較高的電壓使用率、較低的切換損失、與較小的諧波失真。 三階變頻器開關元件所承受的電壓為直流側電壓之半，且在相同的切換頻率下較傳統的二階變頻器有較少的輸出電壓諧波成分，因此三階變頻器適用於高功率的交流驅動器。 我們已成功建立以FPGA 和 PC 為基礎的三階變頻器研究雛型。PC軟體產生SVPWM責任週期和計算空間電壓向量的位置，FPGA負責SVPWM波形產生與延遲時間補償。系統中的切換頻率與延遲時間補償都是可程式的。在三階變頻器的控制系統中，為了減少輸出電壓的諧波成分已研究出四種可行的開關模組。在本系統中也詳細考慮了中間電壓的不平衡問題，利用簡化的馬達模型討論開關狀態對中間電壓的影響。在本論文中提出中間電壓的補償辦法有助於控制中間電壓的穩定。模擬與實驗結果都證實SVPWM之三階變頻器的可行性。

The thesis presents a three-level inverter research based on the space vector pulse width modulation( SVPWM ) strategy .The SVPWM theorem was chosen owing to higher voltage utility，lower switching loss and lower harmonic distortion comparing to SPWM( Sinusoidal Pulse Width Modulation ) theorem. Three-level inverter is suitable for large capacity and high voltage AC drives, since the blocking voltage of each switching devices is clamped to half of Dc-link voltage and harmonic component of the output voltage is less then those of the conventional two-level inverter at the same switching frequency. We have made the three-level inverter modal based on PC and FPGA successfully. The PC software generates SVPWM duty and calculates the position of space voltage vector. FPGA is responsible for SVPWM waveform generation and delay-time compensation. The switching frequency and the delay-time compensation in this system are programmable In controlling three-level inverter system, four switching patterns have been studied in order to minimize the harmonic components of the output voltage. The problem of neutral-point DC voltage unbalance is considered carefully in this system. The influence of switching states on neural point DC voltage is discussed based on a simplified motor modal. The compensation method of neural point DC voltage proposed in this paper help to control the stability of neutral voltage. Simulation and experimental results are given to verify the realization of SVPWM three-level inverter.