在僅用快取記憶體多處理機系統中降低錯誤分享的影響和資料區塊取代的延遲的研究及其模擬評估環境之研製

Abstract

僅用快取記憶體多處理機架構主要是為了當快取記憶體大小不能滿足大部份的存取需求。因此, 它提供資料區塊的複製和遷移的功能，使得資料區塊能存在較多的處理單元內，來滿足較多的存取需求。但是，資料一致性的存取失誤將會嚴重降低它的效能，因為它的快取記憶體架構使得執行遠端存取需要較大的負擔。錯誤分享的存取失誤是一種資料一致性的存取失誤，而且是可以避免且不需要出現。因此，減少錯誤分享的存取失誤是一項非常重要的課題。另外，因為僅用快取記憶體多處理機架構並沒有共享記憶體的機制，所以當最後一個有效區塊被取代時，我們需要從其他的處理單元找到位子來儲存它。在這篇論文當中，我們利用子區塊機制來減少錯誤分享的存取失誤，並且提出幾個取代方法來減少取代的延遲時間。最後，我們將這些方法整合在一起，在我們的評估結果，這種整合的方法平均可以降低5%的執行時間。詳細的設計原理與效能評估將在論文各章節中一一的說明。

F-COMA is designed to promote hit rate, while local cache is not large enough to serve most accesses. Thus, it provides data replication and migration, and let each processor access the requested data block locally. Unfortunately too many coherence misses will drop down the performance of F-COMA, because remote accesses have critical latency. False sharing miss is a kind of coherence miss, and it should not happen necessarily. Hence, it is important to reduce false sharing misses in F-COMA. Because there is no memory in F-COMA, we must reserve the last valid block while it is replaced. In this thesis, we use sub-block mechanism to reduce the impact of false sharing, and some replacement techniques to reduce replacement stall time. Based on our evaluation results, we have shown that these two methods speedup the total performance about 5% in average under SPLASH benchmarks. The detailed information about design principles and performance evaluations will be described in the literature.