使用差和調變之真實均方根轉換器

Abstract

對於一個交流或者受到干擾的直流輸入信號，真實均方根轉換器提供一個等效於其均方根值之等效直流輸出電壓值。而且，差和調變器﹝DS Modulator﹞在混合式積體電路廣泛的使用，已經證明了此調變器可以突破超大型積體電路中天生所存在的類比元件性能的限制。因此，使用差和調變技術的真實均方根轉換器可以被預期的優點，有不僅是和CMOS積體電路整合的彈性，而且也可以相當程度地忍受元件的不完美特性。在這篇論文裡，我們描述了一個基於超取樣技術的架構，來在CMOS製程中實現一個低成本的真實均方根轉換器。 為了建構一個差和式真實均方根轉換器，我們以把參考電壓端視為可變的輸入來擴展差和式調變器的使用，並提出了一個新的模型來描述一個差和式調變器在參考電壓變動時的行為。因為這個新模型可以被應用不僅於差和式真實均方根轉換器而且於參考端受到雜訊信號干擾之傳統之差和式調變器，所以這個新模型可以被發現是比傳統的線性模型還基本。所提出轉換器架構的信號對量化雜訊比和轉移特性一樣都可以基於這個模型而推導出來獲得初步的設計參數。 所提架構的測試晶片已經成功地被實現於0.8mm之有電容雙金屬(DPDM) 之CMOS製程中，並佔面積約為1 mm^2。在這晶片中，使用了非直接電荷轉換技術(IDCT) 來使得轉換器之增益只和晶片上的電容比例有關，降低了增益飄遺憾提供了好的精確度。量測結果顯示，這個轉換器的信號雜訊比達到88dB，而且對於波峰因子﹝Crest Factor﹞到達3的任意波形量測，其相對精確度為±0.2%。在沒有調整和校正的情況下，祝轉換器的絕對增益誤差小於±0.4%。這個轉換器非常適合被整合於做功率量測、雜訊量測和感測器輸出信號量測等量測系統CMOS晶片中。

A true rms converter provides a dc output equal to the rms value of an ac or fluctuating dc input, and the extensive use of delta-sigma (DS) modulators in mixed-mode integrated circuits (ICs) has shown promise for coping with the analog component limitations inherent in VLSI technologies. A true rms converter using DS modulation thus is expected to have the advantages of not only CMOS integration flexibility but also being robustness against circuit elements imperfections. In this dissertation, we present a new architecture based on oversampling technique to realize a low-cost true rms converter in CMOS technologies, especially for a further integration of a handheld DMM chip. To construct a DS true rms converter, we extend the use of the DS modulator by considering the reference as a variable input and propose a new model for describing the behavior of a DS modulator with a variable reference. This new model will be found to be more essential than traditional linear model since it can be applied to analyze the behavior of not only DS true rms converters but also traditional DS modulators with reference interfered by a random signal. Based on this model, the signal-to-quantization-noise ratio (SQNR) as well as transfer characteristics of the proposed architecture have been deduced to obtain initial design parameters. A test chip of the proposed converter was successfully fabricated in a 0.8mm double-poly double-metal (DPDM) CMOS process and occupies active area of 1 mm2. The use of indirect charge transfer (IDCT) technique makes the converter gain depend only on an on-chip capacitor ratio, reducing gain drift and offering good gain accuracy. Measured results show that this converter achieves a SNR of 88 dB and a relative error of ±0.2% for arbitrary inputs with a signal crest factor up to 3. The signal bandwidth exceeds 50 kHz and the full-scale input range is greater than 0.4 Vrms. Without trimming and calibration, this converter has an absolute gain error less than ±0.4%. 1.1. STATE OF THE ART 2 1.1.1. Comparing Methods 2 1.1.2. Computing Methods 5 1.2. TRUE RMS CONVERSION WITH DS MODULATION 7 1.3. ORGANIZATION 9 Chapter 2. A New Model of DS Modulation 10 2.1. ANALYTICAL MODEL 12 2.2. SPECTRAL ANALYSIS 15 2.3. SIMULATION RESULTS 18 Chapter 3. Architecture and Design 25 3.1. CONVERTER ARCHITECTURE 25 3.1.1. DS Divider 26 3.1.2. DS Multiplier-Divider 28 3.1.3. DS TRMS Converter 31 3.2. DESIGN CONSIDERATION 33 3.2.1. Crest Factor 33 3.2.2. Noise 33 3.2.3. Linearity 34 3.2.4. Response Time 36 Chapter 4. Implementation and Experimental Results 38 4.1. ULTRA LARGE TIME-CONSTANT SC FILTERS 38 4.1.1. Traditional Lossy Integrator 40 4.1.2. Indirect Charge Transfer Filter 42 4.2. A FULL DIFFERENTIAL SWITCHED-CAPACITOR IMPLEMENTATION 43 4.2.1. 1-bit Multiplying DAC with an IDCT Filter 44 4.2.2. Phase-Compensated SC DS Divider 46 4.2.3. Complete SC DS TRMS Converter 47 4.3. EXPERIMENTAL RESULTS 50 Chapter 5. Conclusion 55 Appendix A. 58 Bibliography 58