互補式金氧半兩段式高速類比至數位轉換器之研究與分析

Abstract

本論文提出一個5伏，8位元，25Ms/sec的互補式金氧半類比至數位轉換器。此類比至數位轉換器是以兩段式(two-step)的架構來實現。此結構主要包含約略比較器(coarse comparator)，精密比較器(fine comparator)，數位錯誤修正電路(digital error correction circuit)，切換開關矩陣電路(switch array circuit)和時脈產生器(clock generator)。 輸出的八個位元中，前面五個高位元是由約略比較所決定，切換開關矩陣電路根據約略比較的結果決定精密比較器的參考電壓值。精密比較除了決定後面三個低位元外，並提供一個位元作為約略比較結果的錯誤修正用。內部電路所需的時脈完全由時脈產生器產生，外部輸入的參考時脈為25MHz。約略比較器的比較速度是精密比較器的兩倍，可以藉由平行處理的方式達到同步。此類比至數位轉換器工作在0伏∼5伏，參考電壓及輸入電壓限制在0伏∼1伏之間，經由HSPICE模擬符合八位元的解析度與25MHz的輸出率，以tsmc 0.6微米製程完成1800x1800微米平方的單一積體電路。

This thesis proposes a 5Volt, 8bits, 25MS/sec CMOS A/D converter which is implemented by the two–step architecture. This structure consists of coarse comparators, fine comparators, digital error correction circuit, switch array circuit and clock generator. Among the eight bits of the output, the coarse comparison determines the 5 MSB bits. The switch array circuit uses the result of coarse comparison to determine the reference voltage of the fine comparators. The fine comparison determines the 3LSB bits and provides one bit to error correction of coarse comparison. The clocks of the circuit are generated by the clock generator and the input reference clock is 25MHz. The speed of the coarse comparators is twice that of the fine comparators, but they can be synchronized by parallel processing. The A/D converter is operating between 0V and 5V. Its reference and input voltage are limited between 0V and 1V. The HSPICE simulation shows that A/D converter has a resolution of 8 bits and the throughput rate can be 25MHz. It is completely implemented in single chip with active area about 1800umX1800um by tsmc 0.6um process. Abstract in English………………………………………………………ii Acknowledgement………………………………………………………… iii Contents…………………………………………………………………… iv Figure Captions……………………………………………………………vi Chapter 1 Introduction………………………………………………… 1 Chapter 2 System architecture and operating principle…………4 Chapter 3 Design and analysis of the A/D converter circuits…6 3-1 Cosrse comparator and fine comparator……………………… 6 3-2 Transition point detector……………………………………… 9 3-3 Digital Error Correction……………………………………… 10 3-4 Coarse encoder and fine encoder…………………………… 12 3-5 Parallel processing and Timing description……………… 14 Chapter 4 Layout considerations………………………………… 16 Chapter 5 Conclusion and perpectives…………………………… 18 5-1 Conclusion………………………………………………………… 18 5-2 Perspectives……………………………………………………… 18 Reference………………………………………………………………… 20 Figures Table VITA