高效能二維反掃描離散餘弦函數處理器分析與設計

Abstract

反離散餘弦轉換函數(IDCT)已經廣泛地運用在許多視訊壓縮技巧上，而且成為許多國際標準的核心部分。隨著製程技術的進步，單晶片系統設計己套用在許多應用層面上。從系統層面著手來設計模組成了一個愈來愈重要的課題。因此，在本論文中，基於內嵌式反離散餘弦模組的系統需求，我們提出了一個應用於一般數位即時解碼視訊系統及三維電腦繪圖壓縮系統的低成本、高效能的二維反掃描離散餘弦轉換函數架構。此架構具有低複雜度、低通訊複雜度等特性，因此適合於超大型積體電路的製作。 在TSMC 0.35□m 1P4M CMOS製程技術下及使用Avanti 0.35□m的標準元作庫，此架構使用約192K個電晶體，晶片核心面積為2.5□2.5mm2。測試結果顯示本架構之晶片時脈速度可達77MHz，且此晶片可以處理400Mpixel/s 以上的資料量。此外，為了使此模組能重複使用且縮短設計時間，我們提出一個多重模式的架構。此架構可以針對不同的需求，在最短的時間內得到最佳的反離散餘弦函數模組。

Inverse discrete cosine transform (IDCT) had been widely used in many video and graphic decompression system and plays a fundamental role in several international standards. Due to the computational intensity of the IDCT, dedicated ASIC solutions are required for implementation. With the development of silicon technology, system on chip (SOC) has been realized in many applications. Design a module must consider the problem in system integration. So designing in system level is a more and more important topic. In system level, opitimizing each function blocks are significant as reducing the extra buffers of interface. In this thesis, based on the requirements of real-time video codec system and 3-D graphic texture compression system, and analysis results of compressed data, a low-cost and high-performance inverse scan DCT architecture is proposed for application of a real-time digital video decode system and a 3-D graphic texture decompression system. It owns VLSI-suitable properties such as low complexity and uncomplicated communication. Based on TSMC 0.35 □m 1P4M CMOS technology and Avanti 0.35□m cell library, our proposed architecture is implemented. It integrates about 192K transistors and the core occupies a silicon area of 2.5 □ 2.5mm2. The IMS testing result shows that the clock rate can be up to about 77MHz. The chip can achieve 400Mpixel/s data rate and higher. Besides, in order to make the architecture reusable, a modified version of IDCT is proposed for reusable purpose. 1.1 Overview of DCT-Based Compression 1.2 Motivation 1.3 Organization of this thesis Chapter 2 IDCT in Digital Video Codec System and 3-D Graphic System 2.1 Overview of MPEG-2 Decode System 2.1.1 MPEG-2 Codec System 2.1.2 Overview of Compression Algorithm 2.1.3 Decoding Process 2.1.3.1 Inverse Quantization Module 2.1.3.2 Inverse Scan Module 2.1.4 Profiles and Levels - 2.2 Overview of 3-D Graphic Texture Compression ystem 2.3 System Requirement 2.3.1 Requirements of MPEG-2 Decoder 2.3.2 Requirements of 3-D Graphic Texture Compression System 2.4 History of Inverse Discrete Cosine Transform 2.4.1 Not Row-Column Algorithm’s (NRCA’s) 2.4.2 Row-Column Algorithm’s (RCA’s) 2.5 Structure of Inverse Scan Discrete Cosine Transform 2.5.1 Data Feature 2.5.2 Architecture of Inverse Scan and IDCT 2.5.3 Comparison Chapter 3 Algorithm and Architecture 3.1 Algorithm Description 3.1.1 First 1-D ISDCT 3.1.2 Second 1-D ISDCT 3.2 Architecture Design 3.2.1 First 1-D ISDCT 3.2.2 Transpose Memory 3.2.3 Second 1-D ISDCT 3.3 Optimization 3.3.1 Constant Multiplier 3.3.2 Finite Wordlength Simulation 3.4 Design Flow 3.5 Post-layout Simulation 3.6 Implementation Results 3.7 Comparison Chapter 4 IP-Based Design 4.1 Integration of System- On-Chip Design 4.1.1 Design with Soft Modules 4.1.2 Design with Hard Modules 4.2 Implementing a Reuse Process 4.2.1 Steps in Implementing a Reuse Process 4.2.2 Dealing with Legacy Designs 4.3 Multi-mode IDCT Chapter 5 Conclusion and Future Work 5.1 Conclusion 5.2 Future Work