完整後設資料紀錄
DC 欄位語言
dc.contributor.author蔣和泰en_US
dc.contributor.authorHe-Tai Jiangen_US
dc.contributor.author吳錦川en_US
dc.contributor.authorDr. Jiin-Chuan Wuen_US
dc.date.accessioned2014-12-12T02:23:05Z-
dc.date.available2014-12-12T02:23:05Z-
dc.date.issued1999en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT880428026en_US
dc.identifier.urihttp://hdl.handle.net/11536/65659-
dc.description.abstract本論文描述一個3.3V,8位元,25MS/s的類比至數位轉換器。它的輸入電壓限制在0V~1V之間,而參考電壓為0V及1V。此類比至數位轉換器以TSMC 1P4M 0.35微米製程技術來設計。經過HSPICE的模擬符合8位元解析度與每秒25百萬取樣。最後將此類比至數位轉換器製成1500x1600微米平方的單一積體電路。 此類比至數位轉換器是以兩級(two-step)的架構來實現。此結構不需要用到高增益或大輸出擺幅的操作放大器。主要的元件為約略比較器(coarse comparator)及精密比較器(fine comparator)。在此由31個約略比較器輸出5位元運算結果,而16個精密比較器輸出4位元。多出的1位元是作為數位修正之用。zh_TW
dc.description.abstractThis thesis describes a 3.3V, 8-bit, 25Ms/s A/D converter. The input voltage range of this ADC is from 0V to 1V, and the reference voltages are 0V and 1V. The ADC is designed with the TSMC 1P4M 0.35um process. In the simulation result of HSPICE, it has achieved a resolution of 8-bit and the speed of 25Ms/s. The ADC is completely implement in a singal chip with the area about 1500x1600 micro-meter squares. The A/D converter is implement by the two-step architecture. The structure can be designed without either the high gain or a large output swing operational amplifier. The primary components of the ADC are the coarse comparator and fine comparator. There are 31 coarse comparator to generate 5-bit output, and 15 fine comparator to generate 4-bit output. The additional one bit is for digital error correction. Chapter 2 The Architecture of the Two-Step A/D Converter...3 2.1 Operating principle of the two-step A/D converter…….…3 2.2 Description of digital error correction…………………….4 Chapter 3 Design and Analysis of the Circuits……….……6 3.1 Coarse Comparator…..…………………………………………6 3.2 Fine Comparator……………..…………………………………8 3.3 Reference Voltage Generator……………..…………………11 3.4 The Transition Point Detector………………………………12 3.5 The Coarse Encoder…………………………………...………12 3.6 The Fine Encoder……………………………………...………13 3.7 The Digital Error Correction Circuit……………………14 3.8 The Clock Generator………………………………………….15 Chapter 4 Layout Considerations…………………………...16 4.1 Floor-plan of the A/D Converter…………………………16 4.2 Layout Consideration for Mixed-Mode Circuit…………16 4.3 The Layout of Capacitor……………………………………17 Chapter 5 Conclusion and Perspectives……….……………18 5.1 Conclusion……………………..……………….……………18 5.2 Perspectives………………….………………………………19en_US
dc.language.isoen_USen_US
dc.subject類比至數位zh_TW
dc.subject類比至數位轉換器zh_TW
dc.subject轉換器zh_TW
dc.subjectADen_US
dc.subjectADCen_US
dc.subjectConverteren_US
dc.title0.35微米互補式金氧半類比數位轉換器之設計與分析zh_TW
dc.titleDesign and Analysis of a 0.35um CMOS A/D Converteren_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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