針對 Verilog 到 VHDL 轉譯之研究

Abstract

在傳統的硬體描述語言 (Hardware Description Language) 為基礎的設計流程中 , 積體電路設計者在設計電路時通常只利用某一個硬體描述語言 (如 Verilog ). 如今, 由於單晶片系統 (SOC) 以及積體電路設計專利重複利用 (IP-reuse) 的趨勢下, 設計者必須面臨一個同時含有兩種硬體描述語言的設計 (Mixed Language), 也就是同時含有 Verilog 和 VHDL. 如果有一個 Verilog 到 VHDL的轉譯器, 此時設計者可以更容易的處理含有混和語言的設計, 因為他們可以先將 Verilog 的設計先轉成 VHDL 的格式. 在這個論文中, 我們發表了一個 Verilog 到 VHDL 的轉譯器, 它可以處理可合成的 Verilog, 將之轉成 VHDL 格式並不改變其電路的行為. 在這論文中也完整的描述了 Verilog 和VHDL之間的相異處, 以及轉譯器在對於這些相異處所做額外的處理. 為了驗證所轉出來的VHDL 碼, 我們也提出了一個驗證環境來確保原始的 Verilog 設計和轉譯出來的 VHDL 設計的一致性. 在實驗的結果也證明了轉譯器在處理時的正確性和效率.

In the traditional HDL-based design flow, IC designers are ften concentrating on using one HDL for their designs. Now, due to the trend of SOC and IP-reuse, they may have to work with both VHDL and Verilog. If a Verilog to VHDL translator is available, the designers can easily handle those mixed language designs by translating the IPs written in Verilog to VHDL format. In this thesis, we present a Verilog to VHDL transilator that can deal with synthesizable Verilog code and translate it to VHDL format without changing the functionality. The differences between those two HDLs and the extra efforts to translate them are clearly described in this thesis. In order to verify the generated VHDL codes, we also propose a verification environment to ensure the functional consistency between the generated VHDL codes and the original Verilog codes. The experiments on a variety of different designs have shown the correctness and efficiency of our translator. ABSTRACT ACKNOWLEDGEMENTS CONTENTS LIST OF TABLES LIST OF FIGURES 1. INTRODUCTION 3 2. VERILOG TO VHDL TRANSLATION 6 2.1 OVERVIEW 6 2.1.1 Parsing Verilog Code 6 2.1.2 Verilog to VHDL translation 7 2.1.3 Verification Environment 8 2.2 SUPPORTED CONSTRUCTS 8 2.2.1 Design Entity 9 2.2.2 Data Type and Object 10 2.2.3 Declaration 12 2.2.4 Concurrent statement 13 2.2.5 Sequential statement 17 2.2.6 Output signal 26 2.2.7 Operators 27 2.3 SENSITIVITY / EVENT LIST 32 2.4 CONFIGURATION GENERATION 33 2.4.1 Configuration declarations 34 2.4.2 Configuration specifications 34 3. VERIFYING THE VHDL DESIGNS 36 3.1 OUR APPROACH 36 3.2 VERIFICATION WITH DUMP FILE 37 3.3 VERIFICATION ENVIRONMENT 38 4. EXPERIMENTAL RESULTS 40 5. CONCLUSIONS 43 6. FUTURE WORKS 44 REFERENCE 45 List of Tables Table 2.1 : Supported constructs…………………………………………………..……6 Table 2.2 : The comparison between the operators ..…………………………….……26 Table 4.1 : Translation results………………………………………………………….40 List of Figures Figure 1.1 : Typical design flow…………………………………………………………1 Figure 1.2 : Simplified design flow……………………………………………………...2 Figure 2.1 : The overall Flow chart of our V2V translator 6 Figure 2.2 : The Verilog parsing tree 7 Figure 2.3 : The pseudo code of our V2V translator 7 Figure 2.5 : Differences between data types and data objects of Verilog and VHDL 10 Figure 2.6 : Module instantiation translation 16 Figure 2.7 : Always statement translation 16 Figure 2.8 : Continuous assignment translation 17 Figure 2.9 : Blocking assignment translation. 22 Figure 2.10 : A special case of if statement translation. 23 Figure 2.11 : Translate the special if statement 23 Figure 2.12 : Casex and casez statements translation 24 Figure 2.13 : Task statement translation. 25 Figure 2.14 : Function call statement translation. 26 Figure 2.15 : Extra handling for output signal 27 Figure 2.16 : Concatenation operator translation 29 Figure 2.17 : Translation of the concatenation in case statement 30 Figure 2.18 : Replication operator translation 30 Figure 2.19 : Condition operator translation 31 Figure 2.20 : Translation of reduction operator 31 Figure 2.21 : Event list translation 33 Figure 2.19 : The translation flow with automatic configuration generator 34 Figure 3.1 : The system tasks that create VCD files in the Verilog 38 Figure 3.2 : An illustration of the VCD format 38 Figure 3.3 : Our verification environment 39 Figure 4.1 : The stack output waveforms of the Verilog code and the VHDL code 41 Figure 4.2 : The DCT output waveforms of the Verilog code and the VHDL code 42 Figure 4.3 : The VPU output waveforms of the Verilog code and the VHDL code 43